Lines Matching refs:EL1

77    the secure world, managing multiple S-EL1 or S-EL0 partitions.
78 #. EL3 SPMC based on the FF-A specification, managing a single S-EL1 partition
100 - Alternatively, SPMC can refer to an S-EL1 component, itself being a secure
112 S-EL1 or S-EL2:
116 - The same SPMD component is used for both S-EL1 and S-EL2 SPMC configurations.
121 - S-EL1 SPMC for platforms not supporting the FEAT_SEL2 architecture
122   extension. The SPMD relays the FF-A protocol from EL3 to S-EL1.
141 SPMC located at S-EL1, S-EL2 or EL3:
152   exception level is set to S-EL1.
167 | SPMC at S-EL1 |         0            |        0         |      0      |
193 Sample TF-A build command line when the SPMC is located at S-EL1
430 - The SPMC resides at S-EL1: the SPMC manifest is used by the SPMD to setup a
431   SP that co-resides with the SPMC and executes at S-EL1 or Secure Supervisor
434   the environment required by the SPMC to run at S-EL2. SPs run at S-EL1 or
567 - Memory regions are mapped in the SP EL1&0 Stage-2 translation regime at
568   load time (or EL1&0 Stage-1 for an S-EL1 SPMC). A memory region node can
571 - Device regions are mapped in the SP EL1&0 Stage-2 translation regime (or
572   EL1&0 Stage-1 for an S-EL1 SPMC) as peripherals and possibly allocate
576 provided the SPMC identity maps IPAs to PAs within SP EL1&0 Stage-2 translation
583 non-secure EL1&0 Stage-2 table if it exists.
624 mapped to the SP secure EL1&0 Stage-2 translation regime. As such, the SP can
806 - Hypervisor or OS kernel in NS-EL1/EL2: the SPMD returns the SPMC version
809 - SPMC at S-EL1/S-EL2: the SPMD returns its own implemented version.
827 receive buffers described by their IPAs to the SP EL1&0 Stage-2 translation
1040 With secure virtualization enabled (``HCR_EL2.VM = 1``) and for S-EL1
1042 secure EL1&0 Stage-1 translation.
1043 The EL1&0 Stage-2 translation hardware is fed by:
1045 - A secure IPA when the SP EL1&0 Stage-1 MMU is disabled.
1046 - One of secure or non-secure IPA when the secure EL1&0 Stage-1 MMU is enabled.
1143   - In the current implementation, S-EL1 SPs are expected to use the para
1147     S-EL1 SPs managed by SPMC.
1170 to S-EL1 SPs. When normal world execution is preempted by a secure interrupt,
1205 In the current implementation, S-EL1 SPs use the para-virtualized HVC interface
1375   guarded in the EL1&0 Stage-1 translation regime.
1503 S-EL0 partitions are presented, loaded and initialized the same as S-EL1 VMs by