Lines Matching refs:secure
9 at the highest secure privileged mode, which is EL3 in AArch64 or Secure SVC/
10 Monitor mode in AArch32, and provides runtime services to the non-secure world.
36 #. Call ``psci_prepare_next_non_secure_ctx()`` to initialize the non-secure CPU
39 #. Get the non-secure ``cpu_context_t`` for the current CPU by calling
40 ``cm_get_context()`` , then programming the registers in the non-secure
41 context and exiting to non-secure world. If the EL3 Runtime Software needs
42 additional configuration to be set for non-secure context, like routing
43 FIQs to the secure world, the values of the registers can be modified prior
56 initializes/restores the non-secure CPU context as well.
76 PSCI library is in charge of initializing/restoring the non-secure CPU system
80 ``cpu_context_t`` data structure. The initialization of other non-secure CPU
109 information) for exit into non-secure world. Using ``cpu_context_t`` as an
111 values safely until it is ready for exit to non-secure world.
145 The PSCI library is responsible for initializing/restoring the non-secure world
147 non-secure system registers. The PSCI generic code takes care not to directly
148 modify any of the system registers affecting the secure world and instead
154 PSCI library needs the flexibility to access both secure and non-secure
217 After ``psci_setup()`` and prior to exit to the non-secure world, this function
218 must be called by the EL3 Runtime Software to initialize the non-secure world
219 context. The non-secure world entrypoint information ``next_image_info`` (first
220 argument) will be used to determine the non-secure context. After this function
223 to the non-secure world.
259 secure or non-secure world. The ``cookie`` (6th argument) and the ``handle``
276 `PSCI spec`_. For AArch32, on wakeup from power down the CPU resets to secure SVC
288 - Restores/Initializes the non-secure context and populates the
292 non-secure ``cpu_context_t`` using ``cm_get_context()`` and program the registers
293 prior to exit to the non-secure world.
347 choose a more optimal implementation (like dedicating the secure TPIDRPRW
362 by ``cpu_idx`` (first argument). The ``security_state`` will always be non-secure
382 will always be non-secure when called by PSCI library and this argument
397 always be non-secure when called by PSCI library and this argument is
451 use of secure interrupts, then these interrupts must also be managed
452 appropriately during CPU power down/power up. Any secure interrupt targeted
499 in `PSCI spec`_. If the secure payload is a Uniprocessor (UP)
502 ignored if the secure payload is a multiprocessor (MP) implementation.
506 This callback is only relevant if the secure payload in EL3 Runtime
510 API. This callback is never called if the secure payload is a