Lines Matching refs:reset
172 The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
173 the secondary CPUs holding pen to work properly. Unfortunately, its reset value
358 Running on the Foundation FVP with reset to BL1 entrypoint
395 Running on the AEMv8 Base FVP with reset to BL1 entrypoint
419 Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
447 Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
465 Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
484 Running on the AEMv8 Base FVP with reset to BL31 entrypoint
519 - Since a FIP is not loaded when using BL31 as reset entrypoint, the
532 reset vector for each core.
540 Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
581 Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
609 Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint