Lines Matching refs:SUNXI_R_RSB_BASE
42 reg = mmio_read_32(SUNXI_R_RSB_BASE + offset); in rsb_wait_bit()
60 reg = mmio_read_32(SUNXI_R_RSB_BASE + RSB_STAT); in rsb_wait_stat()
71 mmio_write_32(SUNXI_R_RSB_BASE + RSB_CTRL, 0x01); /* soft reset */ in rsb_init_controller()
80 mmio_write_32(SUNXI_R_RSB_BASE + RSB_CMD, RSBCMD_RD8); /* read a byte */ in rsb_read()
81 mmio_write_32(SUNXI_R_RSB_BASE + RSB_SADDR, rt_addr << 16); in rsb_read()
82 mmio_write_32(SUNXI_R_RSB_BASE + RSB_DADDR0, reg_addr); in rsb_read()
83 mmio_write_32(SUNXI_R_RSB_BASE + RSB_CTRL, 0x80);/* start transaction */ in rsb_read()
89 return mmio_read_32(SUNXI_R_RSB_BASE + RSB_DATA0) & 0xff; /* result */ in rsb_read()
94 mmio_write_32(SUNXI_R_RSB_BASE + RSB_CMD, RSBCMD_WR8); /* byte write */ in rsb_write()
95 mmio_write_32(SUNXI_R_RSB_BASE + RSB_SADDR, rt_addr << 16); in rsb_write()
96 mmio_write_32(SUNXI_R_RSB_BASE + RSB_DADDR0, reg_addr); in rsb_write()
97 mmio_write_32(SUNXI_R_RSB_BASE + RSB_DATA0, value); in rsb_write()
98 mmio_write_32(SUNXI_R_RSB_BASE + RSB_CTRL, 0x80);/* start transaction */ in rsb_write()
105 mmio_write_32(SUNXI_R_RSB_BASE + RSB_PMCR, in rsb_set_device_mode()
125 mmio_write_32(SUNXI_R_RSB_BASE + RSB_CCR, reg); in rsb_set_bus_speed()
133 mmio_write_32(SUNXI_R_RSB_BASE + RSB_SADDR, hw_addr | (rt_addr << 16)); in rsb_assign_runtime_address()
134 mmio_write_32(SUNXI_R_RSB_BASE + RSB_CMD, RSBCMD_SRTA); in rsb_assign_runtime_address()
135 mmio_write_32(SUNXI_R_RSB_BASE + RSB_CTRL, 0x80); in rsb_assign_runtime_address()