Lines Matching refs:reg_val
194 uint32_t reg_val; in chal_sd_init() local
207 reg_val = 0; in chal_sd_init()
208 reg_val |= (1 << ICFG_SDIO0_CAP0__SLOT_TYPE_R); in chal_sd_init()
209 reg_val |= (0 << ICFG_SDIO0_CAP0__INT_MODE_R); in chal_sd_init()
210 reg_val |= (0 << ICFG_SDIO0_CAP0__SYS_BUS_64BIT_R); in chal_sd_init()
211 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_1P8V_R); in chal_sd_init()
212 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_3P0V_R); in chal_sd_init()
213 reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_3P3V_R); in chal_sd_init()
214 reg_val |= (1 << ICFG_SDIO0_CAP0__SUSPEND_RESUME_R); in chal_sd_init()
215 reg_val |= (1 << ICFG_SDIO0_CAP0__SDMA_R); in chal_sd_init()
216 reg_val |= (1 << ICFG_SDIO0_CAP0__HIGH_SPEED_R); in chal_sd_init()
217 reg_val |= (1 << ICFG_SDIO0_CAP0__ADMA2_R); in chal_sd_init()
218 reg_val |= (1 << ICFG_SDIO0_CAP0__EXTENDED_MEDIA_R); in chal_sd_init()
219 reg_val |= (2 << ICFG_SDIO0_CAP0__MAX_BLOCK_LEN_R); in chal_sd_init()
220 reg_val |= (0xd0 << ICFG_SDIO0_CAP0__BASE_CLK_FREQ_R); in chal_sd_init()
221 reg_val |= (1 << ICFG_SDIO0_CAP0__TIMEOUT_UNIT_R); in chal_sd_init()
222 reg_val |= (0x30 << ICFG_SDIO0_CAP0__TIMEOUT_CLK_FREQ_R); in chal_sd_init()
224 mmio_write_32(ICFG_SDIO0_CAP0, reg_val); in chal_sd_init()
226 reg_val = 0; in chal_sd_init()
227 reg_val |= (1 << ICFG_SDIO0_CAP1__SPI_BLOCK_MODE_R); in chal_sd_init()
228 reg_val |= (1 << ICFG_SDIO0_CAP1__SPI_MODE_R); in chal_sd_init()
229 reg_val |= (0 << ICFG_SDIO0_CAP1__CLK_MULT_R); in chal_sd_init()
230 reg_val |= (0 << ICFG_SDIO0_CAP1__RETUNING_MODE_R); in chal_sd_init()
231 reg_val |= (1 << ICFG_SDIO0_CAP1__TUNE_SDR50_R); in chal_sd_init()
232 reg_val |= (1 << ICFG_SDIO0_CAP1__TIME_RETUNE_R); in chal_sd_init()
233 reg_val |= (1 << ICFG_SDIO0_CAP1__DRIVER_D_R); in chal_sd_init()
234 reg_val |= (1 << ICFG_SDIO0_CAP1__DRIVER_C_R); in chal_sd_init()
235 reg_val |= (1 << ICFG_SDIO0_CAP1__DRIVER_A_R); in chal_sd_init()
236 reg_val |= (1 << ICFG_SDIO0_CAP1__DDR50_R); in chal_sd_init()
237 reg_val |= (1 << ICFG_SDIO0_CAP1__SDR104_R); in chal_sd_init()
238 reg_val |= (1 << ICFG_SDIO0_CAP1__SDR50_R); in chal_sd_init()
240 mmio_write_32(ICFG_SDIO0_CAP1, reg_val); in chal_sd_init()