Lines Matching refs:sdRegBaseAddr
87 mmio_clrsetbits_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_power()
101 rc = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_power()
119 mmio_setbits_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET, in chal_sd_set_power()
123 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET, 0); in chal_sd_set_power()
124 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET, 0); in chal_sd_set_power()
132 rc = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_power()
164 mmio_clrsetbits_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_dma_boundary()
175 handle->ctrl.sdRegBaseAddr = sdBase; in chal_sd_setup_handler()
252 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_init()
256 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET, in chal_sd_init()
260 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN1_OFFSET, in chal_sd_init()
262 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN2_OFFSET, in chal_sd_init()
267 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN1_OFFSET, in chal_sd_init()
269 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN2_OFFSET, in chal_sd_init()
273 cap_val_l = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_init()
291 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_init()
309 mmio_setbits_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_speed()
314 mmio_clrbits_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_speed()
349 if (caps & mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_check_cap()
398 return (mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_get_atuo12_error()
414 return mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_get_present_status()
431 ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_config_bus_width()
452 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET, in chal_sd_config_bus_width()
482 val = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_dma()
486 mmio_write_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_dma()
512 return (uintptr_t)mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_get_dma_addr()
537 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_BLOCK_OFFSET, in chal_sd_send_cmd()
541 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET, in chal_sd_send_cmd()
553 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET, in chal_sd_send_cmd()
573 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_SYSADDR_OFFSET, in chal_sd_set_dma_addr()
630 value = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_clock()
636 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET, in chal_sd_set_clock()
651 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET, in chal_sd_set_clock()
656 value = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_clock()
672 value = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_clock()
678 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET, in chal_sd_set_clock()
710 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_SYSADDR_OFFSET, in chal_sd_setup_xfer()
750 mmio_write_32(handle->ctrl.sdRegBaseAddr + in chal_sd_write_buffer()
766 mmio_write_32(handle->ctrl.sdRegBaseAddr + in chal_sd_write_buffer()
805 mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_read_buffer()
811 value = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_read_buffer()
846 control = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_reset_line()
849 mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET, in chal_sd_reset_line()
854 control = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_reset_line()
873 resp[0] = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_get_response()
875 resp[1] = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_get_response()
877 resp[2] = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_get_response()
879 resp[3] = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_get_response()
900 mmio_write_32(handle->ctrl.sdRegBaseAddr + in chal_sd_clear_pending_irq()
903 } while (mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_clear_pending_irq()
921 return (mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_get_irq_status()
939 mmio_write_32(handle->ctrl.sdRegBaseAddr + in chal_sd_clear_irq()
943 mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_clear_irq()
991 while (mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_dump_fifo()
993 mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_dump_fifo()
1012 mmio_setbits_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_irq_signal()
1015 mmio_clrbits_32(handle->ctrl.sdRegBaseAddr + in chal_sd_set_irq_signal()