Lines Matching refs:SETR_32
85 SETR_32(SD_INFO1, 0x00000000U); /* all interrupt clear */ in emmc_dev_finalize()
86 SETR_32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */ in emmc_dev_finalize()
87 SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ in emmc_dev_finalize()
88 SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ in emmc_dev_finalize()
89 SETR_32(SD_CLK_CTRL, 0x00000000U); /* MMC clock stop */ in emmc_dev_finalize()
113 SETR_32(SD_INFO1, 0x00000000U); /* all interrupt clear */ in emmc_dev_init()
114 SETR_32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */ in emmc_dev_init()
115 SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ in emmc_dev_init()
116 SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ in emmc_dev_init()
118 SETR_32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */ in emmc_dev_init()
119 SETR_32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */ in emmc_dev_init()
120 SETR_32(SD_CLK_CTRL, 0x00000000U); /* Disable Automatic Control & Clock Output */ in emmc_dev_init()