Lines Matching refs:U
16 #define MIDR_IMPL_MASK U(0xff)
17 #define MIDR_IMPL_SHIFT U(0x18)
18 #define MIDR_VAR_SHIFT U(20)
19 #define MIDR_VAR_BITS U(4)
20 #define MIDR_VAR_MASK U(0xf)
21 #define MIDR_REV_SHIFT U(0)
22 #define MIDR_REV_BITS U(4)
23 #define MIDR_REV_MASK U(0xf)
24 #define MIDR_PN_MASK U(0xfff)
25 #define MIDR_PN_SHIFT U(0x4)
33 #define MPIDR_AFFINITY_BITS U(8)
35 #define MPIDR_AFF0_SHIFT U(0)
36 #define MPIDR_AFF1_SHIFT U(8)
37 #define MPIDR_AFF2_SHIFT U(16)
38 #define MPIDR_AFF3_SHIFT U(32)
41 #define MPIDR_AFFLVL_SHIFT U(3)
60 #define MPIDR_MAX_AFFLVL U(2)
75 #define INVALID_MPID U(0xFFFFFFFF)
128 #define CNTCR_OFF U(0x000)
129 #define CNTCV_OFF U(0x008)
130 #define CNTFID_OFF U(0x020)
132 #define CNTCR_EN (U(1) << 0)
133 #define CNTCR_HDBG (U(1) << 1)
140 #define LOUIS_SHIFT U(21)
141 #define LOC_SHIFT U(24)
142 #define CTYPE_SHIFT(n) U(3 * (n - 1))
143 #define CLIDR_FIELD_WIDTH U(3)
146 #define LEVEL_SHIFT U(1)
149 #define DCISW U(0x0)
150 #define DCCISW U(0x1)
154 #define DCCSW U(0x2)
158 #define ID_AA64PFR0_EL0_SHIFT U(0)
159 #define ID_AA64PFR0_EL1_SHIFT U(4)
160 #define ID_AA64PFR0_EL2_SHIFT U(8)
161 #define ID_AA64PFR0_EL3_SHIFT U(12)
163 #define ID_AA64PFR0_AMU_SHIFT U(44)
165 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0)
167 #define ID_AA64PFR0_AMU_V1P1 U(0x2)
171 #define ID_AA64PFR0_GIC_SHIFT U(24)
172 #define ID_AA64PFR0_GIC_WIDTH U(4)
175 #define ID_AA64PFR0_SVE_SHIFT U(32)
178 #define ID_AA64PFR0_SVE_LENGTH U(4)
180 #define ID_AA64PFR0_SEL2_SHIFT U(36)
183 #define ID_AA64PFR0_MPAM_SHIFT U(40)
186 #define ID_AA64PFR0_DIT_SHIFT U(48)
188 #define ID_AA64PFR0_DIT_LENGTH U(4)
189 #define ID_AA64PFR0_DIT_SUPPORTED U(1)
191 #define ID_AA64PFR0_CSV2_SHIFT U(56)
193 #define ID_AA64PFR0_CSV2_LENGTH U(4)
196 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52)
198 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4)
199 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0)
200 #define ID_AA64PFR0_FEAT_RME_V1 U(1)
202 #define ID_AA64PFR0_RAS_SHIFT U(28)
205 #define ID_AA64PFR0_RAS_LENGTH U(4)
213 #define ID_AA64DFR0_TRACEVER_SHIFT U(4)
216 #define ID_AA64DFR0_TRACEVER_LENGTH U(4)
217 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
218 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
219 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1)
220 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4)
223 #define ID_AA64DFR0_PMS_SHIFT U(32)
229 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44)
234 #define ID_AA64DFR0_MTPMU_SHIFT U(48)
239 #define ID_AA64DFR0_BRBE_SHIFT U(52)
244 #define ID_AA64ISAR0_RNDR_SHIFT U(60)
250 #define ID_AA64ISAR1_GPI_SHIFT U(28)
252 #define ID_AA64ISAR1_GPA_SHIFT U(24)
255 #define ID_AA64ISAR1_API_SHIFT U(8)
257 #define ID_AA64ISAR1_APA_SHIFT U(4)
260 #define ID_AA64ISAR1_SB_SHIFT U(36)
268 #define ID_AA64ISAR2_GPA3_SHIFT U(8)
271 #define ID_AA64ISAR2_APA3_SHIFT U(12)
275 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
278 #define PARANGE_0000 U(32)
279 #define PARANGE_0001 U(36)
280 #define PARANGE_0010 U(40)
281 #define PARANGE_0011 U(42)
282 #define PARANGE_0100 U(44)
283 #define PARANGE_0101 U(48)
284 #define PARANGE_0110 U(52)
286 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
292 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
297 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
302 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
307 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
313 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
318 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
325 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
328 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
336 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
339 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20)
341 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4)
343 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
346 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24)
353 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
358 #define ID_AA64PFR1_EL1_BT_SHIFT U(0)
363 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
366 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28)
367 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf)
373 #define MTE_UNIMPLEMENTED U(0)
375 #define MTE_IMPLEMENTED_EL0 U(1)
377 #define MTE_IMPLEMENTED_ELX U(2)
382 #define MTE_IMPLEMENTED_ASY U(3)
387 #define ID_AA64PFR1_EL1_SME_SHIFT U(24)
391 #define ID_PFR1_VIRTEXT_SHIFT U(12)
392 #define ID_PFR1_VIRTEXT_MASK U(0xf)
397 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
398 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
399 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
405 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
406 (U(1) << 4) | (U(1) << 3))
408 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
409 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
410 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
447 #define SCTLR_TCF0_SHIFT U(38)
452 #define SCTLR_TCF0_NO_EFFECT U(0)
454 #define SCTLR_TCF0_SYNC U(1)
456 #define SCTLR_TCF0_ASYNC U(2)
461 #define SCTLR_TCF0_SYNCR_ASYNCW U(3)
463 #define SCTLR_TCF_SHIFT U(40)
467 #define SCTLR_TCF_NO_EFFECT U(0)
469 #define SCTLR_TCF_SYNC U(1)
471 #define SCTLR_TCF_ASYNC U(2)
476 #define SCTLR_TCF_SYNCR_ASYNCW U(3)
480 #define SCTLR_DSSBS_SHIFT U(44)
483 #define SCTLR_TWEDEL_SHIFT U(46)
498 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
499 #define SCR_NSE_SHIFT U(62)
502 #define SCR_TWEDEL_SHIFT U(30)
506 #define SCR_ENTP2_SHIFT U(41)
508 #define SCR_AMVOFFEN_SHIFT U(35)
531 #define SCR_VALID_BIT_MASK U(0x24000002F8F)
538 #define MDCR_SBRBE_SHIFT U(32)
564 #define MDCR_EL2_MTPME (U(1) << 28)
565 #define MDCR_EL2_HLP (U(1) << 26)
567 #define MDCR_EL2_E2TB_EL1 U(0x3)
568 #define MDCR_EL2_HCCD (U(1) << 23)
569 #define MDCR_EL2_TTRF (U(1) << 19)
570 #define MDCR_EL2_HPMD (U(1) << 17)
571 #define MDCR_EL2_TPMS (U(1) << 14)
573 #define MDCR_EL2_E2PB_EL1 U(0x3)
574 #define MDCR_EL2_TDRA_BIT (U(1) << 11)
575 #define MDCR_EL2_TDOSA_BIT (U(1) << 10)
576 #define MDCR_EL2_TDA_BIT (U(1) << 9)
577 #define MDCR_EL2_TDE_BIT (U(1) << 8)
578 #define MDCR_EL2_HPME_BIT (U(1) << 7)
579 #define MDCR_EL2_TPM_BIT (U(1) << 6)
580 #define MDCR_EL2_TPMCR_BIT (U(1) << 5)
581 #define MDCR_EL2_RESET_VAL U(0x0)
584 #define HSTR_EL2_RESET_VAL U(0x0)
585 #define HSTR_EL2_T_MASK U(0xff)
588 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
589 #define CNTHP_CTL_RESET_VAL U(0x0)
594 #define VTTBR_VMID_SHIFT U(48)
596 #define VTTBR_BADDR_SHIFT U(0)
600 #define HCR_AMVOFFEN_SHIFT U(51)
608 #define HCR_RW_SHIFT U(31)
617 #define ISR_A_SHIFT U(8)
618 #define ISR_I_SHIFT U(7)
619 #define ISR_F_SHIFT U(6)
622 #define CNTHCTL_RESET_VAL U(0x0)
623 #define EVNTEN_BIT (U(1) << 2)
624 #define EL1PCEN_BIT (U(1) << 1)
625 #define EL1PCTEN_BIT (U(1) << 0)
628 #define EL0PTEN_BIT (U(1) << 9)
629 #define EL0VTEN_BIT (U(1) << 8)
630 #define EL0PCTEN_BIT (U(1) << 0)
631 #define EL0VCTEN_BIT (U(1) << 1)
632 #define EVNTEN_BIT (U(1) << 2)
633 #define EVNTDIR_BIT (U(1) << 3)
634 #define EVNTI_SHIFT U(4)
635 #define EVNTI_MASK U(0xf)
638 #define TCPAC_BIT (U(1) << 31)
639 #define TAM_SHIFT U(30)
640 #define TAM_BIT (U(1) << TAM_SHIFT)
641 #define TTA_BIT (U(1) << 20)
642 #define ESM_BIT (U(1) << 12)
643 #define TFP_BIT (U(1) << 10)
644 #define CPTR_EZ_BIT (U(1) << 8)
649 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
650 #define CPTR_EL2_TCPAC_BIT (U(1) << 31)
651 #define CPTR_EL2_TAM_SHIFT U(30)
652 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT)
654 #define CPTR_EL2_SMEN_SHIFT U(24)
655 #define CPTR_EL2_TTA_BIT (U(1) << 20)
656 #define CPTR_EL2_TSM_BIT (U(1) << 12)
657 #define CPTR_EL2_TFP_BIT (U(1) << 10)
658 #define CPTR_EL2_TZ_BIT (U(1) << 8)
662 #define VTCR_RESET_VAL U(0x0)
663 #define VTCR_EL2_MSA (U(1) << 31)
666 #define DAIF_FIQ_BIT (U(1) << 0)
667 #define DAIF_IRQ_BIT (U(1) << 1)
668 #define DAIF_ABT_BIT (U(1) << 2)
669 #define DAIF_DBG_BIT (U(1) << 3)
670 #define SPSR_DAIF_SHIFT U(6)
671 #define SPSR_DAIF_MASK U(0xf)
673 #define SPSR_AIF_SHIFT U(6)
674 #define SPSR_AIF_MASK U(0x7)
676 #define SPSR_E_SHIFT U(9)
677 #define SPSR_E_MASK U(0x1)
678 #define SPSR_E_LITTLE U(0x0)
679 #define SPSR_E_BIG U(0x1)
681 #define SPSR_T_SHIFT U(5)
682 #define SPSR_T_MASK U(0x1)
683 #define SPSR_T_ARM U(0x0)
684 #define SPSR_T_THUMB U(0x1)
686 #define SPSR_M_SHIFT U(4)
687 #define SPSR_M_MASK U(0x1)
688 #define SPSR_M_AARCH64 U(0x0)
689 #define SPSR_M_AARCH32 U(0x1)
690 #define SPSR_M_EL2H U(0x9)
692 #define SPSR_EL_SHIFT U(2)
693 #define SPSR_EL_WIDTH U(2)
695 #define SPSR_SSBS_SHIFT_AARCH64 U(12)
697 #define SPSR_SSBS_SHIFT_AARCH32 U(23)
714 #define RMR_EL3_RR_BIT (U(1) << 1)
715 #define RMR_EL3_AA64_BIT (U(1) << 0)
720 #define HI_VECTOR_BASE U(0xFFFF0000)
727 #define TCR_EL1_IPS_SHIFT U(32)
728 #define TCR_EL2_PS_SHIFT U(16)
729 #define TCR_EL3_PS_SHIFT U(16)
735 #define TCR_T0SZ_SHIFT U(0)
736 #define TCR_T1SZ_SHIFT U(16)
781 #define TCR_TG0_SHIFT U(14)
787 #define TCR_TG1_SHIFT U(30)
796 #define MODE_SP_SHIFT U(0x0)
797 #define MODE_SP_MASK U(0x1)
798 #define MODE_SP_EL0 U(0x0)
799 #define MODE_SP_ELX U(0x1)
801 #define MODE_RW_SHIFT U(0x4)
802 #define MODE_RW_MASK U(0x1)
803 #define MODE_RW_64 U(0x0)
804 #define MODE_RW_32 U(0x1)
806 #define MODE_EL_SHIFT U(0x2)
807 #define MODE_EL_MASK U(0x3)
808 #define MODE_EL_WIDTH U(0x2)
809 #define MODE_EL3 U(0x3)
810 #define MODE_EL2 U(0x2)
811 #define MODE_EL1 U(0x1)
812 #define MODE_EL0 U(0x0)
814 #define MODE32_SHIFT U(0)
815 #define MODE32_MASK U(0xf)
816 #define MODE32_usr U(0x0)
817 #define MODE32_fiq U(0x1)
818 #define MODE32_irq U(0x2)
819 #define MODE32_svc U(0x3)
820 #define MODE32_mon U(0x6)
821 #define MODE32_abt U(0x7)
822 #define MODE32_hyp U(0xa)
823 #define MODE32_und U(0xb)
824 #define MODE32_sys U(0xf)
854 #define CTR_CWG_SHIFT U(24)
855 #define CTR_CWG_MASK U(0xf)
856 #define CTR_ERG_SHIFT U(20)
857 #define CTR_ERG_MASK U(0xf)
858 #define CTR_DMINLINE_SHIFT U(16)
859 #define CTR_DMINLINE_MASK U(0xf)
860 #define CTR_L1IP_SHIFT U(14)
861 #define CTR_L1IP_MASK U(0x3)
862 #define CTR_IMINLINE_SHIFT U(0)
863 #define CTR_IMINLINE_MASK U(0xf)
865 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
868 #define CNTP_CTL_ENABLE_SHIFT U(0)
869 #define CNTP_CTL_IMASK_SHIFT U(1)
870 #define CNTP_CTL_ISTATUS_SHIFT U(2)
872 #define CNTP_CTL_ENABLE_MASK U(1)
873 #define CNTP_CTL_IMASK_MASK U(1)
874 #define CNTP_CTL_ISTATUS_MASK U(1)
877 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
878 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
881 #define ESR_EC_SHIFT U(26)
882 #define ESR_EC_MASK U(0x3f)
883 #define ESR_EC_LENGTH U(6)
884 #define ESR_ISS_SHIFT U(0)
885 #define ESR_ISS_LENGTH U(25)
886 #define EC_UNKNOWN U(0x0)
887 #define EC_WFE_WFI U(0x1)
888 #define EC_AARCH32_CP15_MRC_MCR U(0x3)
889 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
890 #define EC_AARCH32_CP14_MRC_MCR U(0x5)
891 #define EC_AARCH32_CP14_LDC_STC U(0x6)
892 #define EC_FP_SIMD U(0x7)
893 #define EC_AARCH32_CP10_MRC U(0x8)
894 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
895 #define EC_ILLEGAL U(0xe)
896 #define EC_AARCH32_SVC U(0x11)
897 #define EC_AARCH32_HVC U(0x12)
898 #define EC_AARCH32_SMC U(0x13)
899 #define EC_AARCH64_SVC U(0x15)
900 #define EC_AARCH64_HVC U(0x16)
901 #define EC_AARCH64_SMC U(0x17)
902 #define EC_AARCH64_SYS U(0x18)
903 #define EC_IABORT_LOWER_EL U(0x20)
904 #define EC_IABORT_CUR_EL U(0x21)
905 #define EC_PC_ALIGN U(0x22)
906 #define EC_DABORT_LOWER_EL U(0x24)
907 #define EC_DABORT_CUR_EL U(0x25)
908 #define EC_SP_ALIGN U(0x26)
909 #define EC_AARCH32_FP U(0x28)
910 #define EC_AARCH64_FP U(0x2c)
911 #define EC_SERROR U(0x2f)
912 #define EC_BRK U(0x3c)
918 #define ESR_ISS_EABORT_EA_BIT U(9)
923 #define RMR_RESET_REQUEST_SHIFT U(0x1)
924 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
931 #define TLBI_ADDR_SHIFT U(12)
939 #define CNTCTLBASE_CNTFRQ U(0x0)
940 #define CNTNSAR U(0x4)
943 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
944 #define CNTACR_RPCT_SHIFT U(0x0)
945 #define CNTACR_RVCT_SHIFT U(0x1)
946 #define CNTACR_RFRQ_SHIFT U(0x2)
947 #define CNTACR_RVOFF_SHIFT U(0x3)
948 #define CNTACR_RWVT_SHIFT U(0x4)
949 #define CNTACR_RWPT_SHIFT U(0x5)
956 #define CNTPCT_LO U(0x0)
958 #define CNTBASEN_CNTFRQ U(0x10)
960 #define CNTP_CVAL_LO U(0x20)
962 #define CNTP_CTL U(0x2c)
965 #define PMCR_EL0_RESET_VAL U(0x0)
966 #define PMCR_EL0_N_SHIFT U(11)
967 #define PMCR_EL0_N_MASK U(0x1f)
969 #define PMCR_EL0_LP_BIT (U(1) << 7)
970 #define PMCR_EL0_LC_BIT (U(1) << 6)
971 #define PMCR_EL0_DP_BIT (U(1) << 5)
972 #define PMCR_EL0_X_BIT (U(1) << 4)
973 #define PMCR_EL0_D_BIT (U(1) << 3)
974 #define PMCR_EL0_C_BIT (U(1) << 2)
975 #define PMCR_EL0_P_BIT (U(1) << 1)
976 #define PMCR_EL0_E_BIT (U(1) << 0)
985 #define ZCR_EL3_LEN_MASK U(0xf)
988 #define ZCR_EL2_LEN_MASK U(0xf)
1000 #define SMCR_ELX_LEN_SHIFT U(0)
1001 #define SMCR_ELX_LEN_MASK U(0x1ff)
1002 #define SMCR_ELX_FA64_BIT (U(1) << 31)
1049 #define MAIR_NORM_OUTER_SHIFT U(4)
1055 #define PAR_F_SHIFT U(0)
1057 #define PAR_ADDR_SHIFT U(12)
1134 #define AMCNTENSET0_EL0_Pn_SHIFT U(0)
1138 #define AMCNTENSET1_EL0_Pn_SHIFT U(0)
1142 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0)
1146 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0)
1150 #define AMCFGR_EL0_NCG_SHIFT U(28)
1151 #define AMCFGR_EL0_NCG_MASK U(0xf)
1152 #define AMCFGR_EL0_N_SHIFT U(0)
1153 #define AMCFGR_EL0_N_MASK U(0xff)
1156 #define AMCGCR_EL0_CG0NC_SHIFT U(0)
1157 #define AMCGCR_EL0_CG0NC_MASK U(0xff)
1158 #define AMCGCR_EL0_CG1NC_SHIFT U(8)
1159 #define AMCGCR_EL0_CG1NC_MASK U(0xff)
1177 #define AMCG1IDR_CTR_SHIFT U(0)
1179 #define AMCG1IDR_VOFF_SHIFT U(16)
1182 #define AMCR_CG1RZ_SHIFT U(17)
1225 #define DISR_A_BIT U(31)
1228 #define ERRIDR_MASK U(0xffff)
1243 #define ERXCTLR_ED_SHIFT U(0)
1244 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT)
1245 #define ERXCTLR_UE_BIT (U(1) << 4)
1247 #define ERXPFGCTL_UC_BIT (U(1) << 1)
1248 #define ERXPFGCTL_UEU_BIT (U(1) << 2)
1249 #define ERXPFGCTL_CDEN_BIT (U(1) << 31)
1302 #define DSU_CLUSTER_PWR_MASK U(1)