Lines Matching refs:ULL
30 #define MPIDR_MT_MASK (ULL(1) << 24)
34 #define MPIDR_AFFLVL_MASK ULL(0xff)
40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
42 #define MPIDR_AFFLVL0 ULL(0x0)
43 #define MPIDR_AFFLVL1 ULL(0x1)
44 #define MPIDR_AFFLVL2 ULL(0x2)
45 #define MPIDR_AFFLVL3 ULL(0x3)
164 #define ID_AA64PFR0_AMU_MASK ULL(0xf)
166 #define ID_AA64PFR0_AMU_V1 ULL(0x1)
169 #define ID_AA64PFR0_ELX_MASK ULL(0xf)
173 #define ID_AA64PFR0_GIC_MASK ULL(0xf)
176 #define ID_AA64PFR0_SVE_MASK ULL(0xf)
177 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1)
181 #define ID_AA64PFR0_SEL2_MASK ULL(0xf)
184 #define ID_AA64PFR0_MPAM_MASK ULL(0xf)
187 #define ID_AA64PFR0_DIT_MASK ULL(0xf)
192 #define ID_AA64PFR0_CSV2_MASK ULL(0xf)
194 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2)
197 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf)
203 #define ID_AA64PFR0_RAS_MASK ULL(0xf)
204 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0)
208 #define EL_IMPL_NONE ULL(0)
209 #define EL_IMPL_A64ONLY ULL(1)
210 #define EL_IMPL_A64_A32 ULL(2)
214 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
215 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1)
224 #define ID_AA64DFR0_PMS_MASK ULL(0xf)
225 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1)
226 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0)
230 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf)
231 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1)
235 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
236 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
240 #define ID_AA64DFR0_BRBE_MASK ULL(0xf)
241 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1)
245 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
251 #define ID_AA64ISAR1_GPI_MASK ULL(0xf)
253 #define ID_AA64ISAR1_GPA_MASK ULL(0xf)
256 #define ID_AA64ISAR1_API_MASK ULL(0xf)
258 #define ID_AA64ISAR1_APA_MASK ULL(0xf)
261 #define ID_AA64ISAR1_SB_MASK ULL(0xf)
262 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1)
263 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0)
269 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf)
272 #define ID_AA64ISAR2_APA3_MASK ULL(0xf)
276 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
287 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
288 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
289 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
290 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
293 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
294 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
295 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
298 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
299 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
300 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
303 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
304 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
305 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
308 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
309 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
310 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
314 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
315 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
316 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
319 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
320 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
321 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
322 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
323 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
326 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
329 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
330 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
331 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0)
337 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
340 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf)
344 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
347 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf)
348 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0)
349 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1)
350 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2)
354 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
356 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
359 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
361 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
364 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
369 #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
370 #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
384 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
385 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
388 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
412 #define SCTLR_M_BIT (ULL(1) << 0)
413 #define SCTLR_A_BIT (ULL(1) << 1)
414 #define SCTLR_C_BIT (ULL(1) << 2)
415 #define SCTLR_SA_BIT (ULL(1) << 3)
416 #define SCTLR_SA0_BIT (ULL(1) << 4)
417 #define SCTLR_CP15BEN_BIT (ULL(1) << 5)
418 #define SCTLR_nAA_BIT (ULL(1) << 6)
419 #define SCTLR_ITD_BIT (ULL(1) << 7)
420 #define SCTLR_SED_BIT (ULL(1) << 8)
421 #define SCTLR_UMA_BIT (ULL(1) << 9)
422 #define SCTLR_EnRCTX_BIT (ULL(1) << 10)
423 #define SCTLR_EOS_BIT (ULL(1) << 11)
424 #define SCTLR_I_BIT (ULL(1) << 12)
425 #define SCTLR_EnDB_BIT (ULL(1) << 13)
426 #define SCTLR_DZE_BIT (ULL(1) << 14)
427 #define SCTLR_UCT_BIT (ULL(1) << 15)
428 #define SCTLR_NTWI_BIT (ULL(1) << 16)
429 #define SCTLR_NTWE_BIT (ULL(1) << 18)
430 #define SCTLR_WXN_BIT (ULL(1) << 19)
431 #define SCTLR_TSCXT_BIT (ULL(1) << 20)
432 #define SCTLR_IESB_BIT (ULL(1) << 21)
433 #define SCTLR_EIS_BIT (ULL(1) << 22)
434 #define SCTLR_SPAN_BIT (ULL(1) << 23)
435 #define SCTLR_E0E_BIT (ULL(1) << 24)
436 #define SCTLR_EE_BIT (ULL(1) << 25)
437 #define SCTLR_UCI_BIT (ULL(1) << 26)
438 #define SCTLR_EnDA_BIT (ULL(1) << 27)
439 #define SCTLR_nTLSMD_BIT (ULL(1) << 28)
440 #define SCTLR_LSMAOE_BIT (ULL(1) << 29)
441 #define SCTLR_EnIB_BIT (ULL(1) << 30)
442 #define SCTLR_EnIA_BIT (ULL(1) << 31)
443 #define SCTLR_BT0_BIT (ULL(1) << 35)
444 #define SCTLR_BT1_BIT (ULL(1) << 36)
445 #define SCTLR_BT_BIT (ULL(1) << 36)
446 #define SCTLR_ITFSB_BIT (ULL(1) << 37)
448 #define SCTLR_TCF0_MASK ULL(3)
449 #define SCTLR_ENTP2_BIT (ULL(1) << 60)
464 #define SCTLR_TCF_MASK ULL(3)
478 #define SCTLR_ATA0_BIT (ULL(1) << 42)
479 #define SCTLR_ATA_BIT (ULL(1) << 43)
481 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT)
482 #define SCTLR_TWEDEn_BIT (ULL(1) << 45)
484 #define SCTLR_TWEDEL_MASK ULL(0xf)
485 #define SCTLR_EnASR_BIT (ULL(1) << 54)
486 #define SCTLR_EnAS0_BIT (ULL(1) << 55)
487 #define SCTLR_EnALS_BIT (ULL(1) << 56)
488 #define SCTLR_EPAN_BIT (ULL(1) << 57)
500 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
503 #define SCR_TWEDEL_MASK ULL(0xf)
535 #define MDCR_EnPMSN_BIT (ULL(1) << 36)
536 #define MDCR_MPMX_BIT (ULL(1) << 35)
537 #define MDCR_MCCD_BIT (ULL(1) << 34)
539 #define MDCR_SBRBE_MASK ULL(0x3)
541 #define MDCR_NSTB_EL1 ULL(0x3)
542 #define MDCR_NSTBE (ULL(1) << 26)
543 #define MDCR_MTPME_BIT (ULL(1) << 28)
544 #define MDCR_TDCC_BIT (ULL(1) << 27)
545 #define MDCR_SCCD_BIT (ULL(1) << 23)
546 #define MDCR_EPMAD_BIT (ULL(1) << 21)
547 #define MDCR_EDAD_BIT (ULL(1) << 20)
548 #define MDCR_TTRF_BIT (ULL(1) << 19)
549 #define MDCR_STE_BIT (ULL(1) << 18)
550 #define MDCR_SPME_BIT (ULL(1) << 17)
551 #define MDCR_SDD_BIT (ULL(1) << 16)
553 #define MDCR_SPD32_LEGACY ULL(0x0)
554 #define MDCR_SPD32_DISABLE ULL(0x2)
555 #define MDCR_SPD32_ENABLE ULL(0x3)
557 #define MDCR_NSPB_EL1 ULL(0x3)
558 #define MDCR_TDOSA_BIT (ULL(1) << 10)
559 #define MDCR_TDA_BIT (ULL(1) << 9)
560 #define MDCR_TPM_BIT (ULL(1) << 6)
561 #define MDCR_EL3_RESET_VAL ULL(0x0)
592 #define VTTBR_RESET_VAL ULL(0x0)
593 #define VTTBR_VMID_MASK ULL(0xff)
595 #define VTTBR_BADDR_MASK ULL(0xffffffffffff)
599 #define HCR_RESET_VAL ULL(0x0)
601 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT)
602 #define HCR_TEA_BIT (ULL(1) << 47)
603 #define HCR_API_BIT (ULL(1) << 41)
604 #define HCR_APK_BIT (ULL(1) << 40)
605 #define HCR_E2H_BIT (ULL(1) << 34)
606 #define HCR_HCD_BIT (ULL(1) << 29)
607 #define HCR_TGE_BIT (ULL(1) << 27)
609 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
610 #define HCR_TWE_BIT (ULL(1) << 14)
611 #define HCR_TWI_BIT (ULL(1) << 13)
612 #define HCR_AMO_BIT (ULL(1) << 5)
613 #define HCR_IMO_BIT (ULL(1) << 4)
614 #define HCR_FMO_BIT (ULL(1) << 3)
653 #define CPTR_EL2_SMEN_MASK ULL(0x3)
696 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
698 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
725 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
726 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
731 #define TCR_TxSZ_MIN ULL(16)
732 #define TCR_TxSZ_MAX ULL(39)
733 #define TCR_TxSZ_MAX_TTST ULL(48)
739 #define TCR_PS_BITS_4GB ULL(0x0)
740 #define TCR_PS_BITS_64GB ULL(0x1)
741 #define TCR_PS_BITS_1TB ULL(0x2)
742 #define TCR_PS_BITS_4TB ULL(0x3)
743 #define TCR_PS_BITS_16TB ULL(0x4)
744 #define TCR_PS_BITS_256TB ULL(0x5)
746 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
747 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
748 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
749 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
750 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
751 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
753 #define TCR_RGN_INNER_NC (ULL(0x0) << 8)
754 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
755 #define TCR_RGN_INNER_WT (ULL(0x2) << 8)
756 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
758 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
759 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
760 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
761 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
763 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
764 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
765 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
767 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
768 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
769 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
770 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
772 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
773 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
774 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
775 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
777 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
778 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
779 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
782 #define TCR_TG0_MASK ULL(3)
783 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
784 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
785 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
788 #define TCR_TG1_MASK ULL(3)
789 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
790 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
791 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
793 #define TCR_EPD0_BIT (ULL(1) << 7)
794 #define TCR_EPD1_BIT (ULL(1) << 23)
849 #define TTBR_CNP_BIT ULL(0x1)
932 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
1010 #define MAIR_DEV_nGnRnE ULL(0x0)
1011 #define MAIR_DEV_nGnRE ULL(0x4)
1012 #define MAIR_DEV_nGRE ULL(0x8)
1013 #define MAIR_DEV_GRE ULL(0xc)
1033 #define MAIR_NORM_WT_TR_WA ULL(0x1)
1034 #define MAIR_NORM_WT_TR_RA ULL(0x2)
1035 #define MAIR_NORM_WT_TR_RWA ULL(0x3)
1036 #define MAIR_NORM_NC ULL(0x4)
1037 #define MAIR_NORM_WB_TR_WA ULL(0x5)
1038 #define MAIR_NORM_WB_TR_RA ULL(0x6)
1039 #define MAIR_NORM_WB_TR_RWA ULL(0x7)
1040 #define MAIR_NORM_WT_NTR_NA ULL(0x8)
1041 #define MAIR_NORM_WT_NTR_WA ULL(0x9)
1042 #define MAIR_NORM_WT_NTR_RA ULL(0xa)
1043 #define MAIR_NORM_WT_NTR_RWA ULL(0xb)
1044 #define MAIR_NORM_WB_NTR_NA ULL(0xc)
1045 #define MAIR_NORM_WB_NTR_WA ULL(0xd)
1046 #define MAIR_NORM_WB_NTR_RA ULL(0xe)
1047 #define MAIR_NORM_WB_NTR_RWA ULL(0xf)
1056 #define PAR_F_MASK ULL(0x1)
1058 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
1135 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff)
1139 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff)
1143 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff)
1147 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff)
1162 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
1163 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
1165 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
1166 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
1168 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
1176 #define AMCG1IDR_CTR_MASK ULL(0xffff)
1178 #define AMCG1IDR_VOFF_MASK ULL(0xffff)
1183 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT)