Lines Matching refs:_h
33 #define SMC_RET0(_h) { \ argument
34 return (uint64_t) (_h); \
36 #define SMC_RET1(_h, _x0) { \ argument
37 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \
38 SMC_RET0(_h); \
40 #define SMC_RET2(_h, _x0, _x1) { \ argument
41 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X1), (_x1)); \
42 SMC_RET1(_h, (_x0)); \
44 #define SMC_RET3(_h, _x0, _x1, _x2) { \ argument
45 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \
46 SMC_RET2(_h, (_x0), (_x1)); \
48 #define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ argument
49 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X3), (_x3)); \
50 SMC_RET3(_h, (_x0), (_x1), (_x2)); \
52 #define SMC_RET5(_h, _x0, _x1, _x2, _x3, _x4) { \ argument
53 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \
54 SMC_RET4(_h, (_x0), (_x1), (_x2), (_x3)); \
56 #define SMC_RET6(_h, _x0, _x1, _x2, _x3, _x4, _x5) { \ argument
57 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \
58 SMC_RET5(_h, (_x0), (_x1), (_x2), (_x3), (_x4)); \
60 #define SMC_RET7(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6) { \ argument
61 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X6), (_x6)); \
62 SMC_RET6(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5)); \
64 #define SMC_RET8(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6, _x7) { \ argument
65 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X7), (_x7)); \
66 SMC_RET7(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5), (_x6)); \
73 #define SMC_GET_GP(_h, _g) \ argument
74 read_ctx_reg((get_gpregs_ctx(_h)), (_g))
75 #define SMC_SET_GP(_h, _g, _v) \ argument
76 write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v))
82 #define SMC_GET_EL3(_h, _e) \ argument
83 read_ctx_reg((get_el3state_ctx(_h)), (_e))
84 #define SMC_SET_EL3(_h, _e, _v) \ argument
85 write_ctx_reg((get_el3state_ctx(_h)), (_e), (_v))