Lines Matching defs:ddr4_spd
49 struct ddr4_spd { struct
51 unsigned char info_size_crc; /* 0 # bytes */
52 unsigned char spd_rev; /* 1 Total # bytes of SPD */
53 unsigned char mem_type; /* 2 Key Byte / mem type */
54 unsigned char module_type; /* 3 Key Byte / Module Type */
55 unsigned char density_banks; /* 4 Density and Banks */
56 unsigned char addressing; /* 5 Addressing */
57 unsigned char package_type; /* 6 Package type */
58 unsigned char opt_feature; /* 7 Optional features */
59 unsigned char thermal_ref; /* 8 Thermal and refresh */
60 unsigned char oth_opt_features; /* 9 Other optional features */
61 unsigned char res_10; /* 10 Reserved */
62 unsigned char module_vdd; /* 11 Module nominal voltage */
63 unsigned char organization; /* 12 Module Organization */
64 unsigned char bus_width; /* 13 Module Memory Bus Width */
65 unsigned char therm_sensor; /* 14 Module Thermal Sensor */
66 unsigned char ext_type; /* 15 Extended module type */
67 unsigned char res_16;
68 unsigned char timebases; /* 17 MTb and FTB */
69 unsigned char tck_min; /* 18 tCKAVGmin */
70 unsigned char tck_max; /* 19 TCKAVGmax */
71 unsigned char caslat_b1; /* 20 CAS latencies, 1st byte */
72 unsigned char caslat_b2; /* 21 CAS latencies, 2nd byte */
73 unsigned char caslat_b3; /* 22 CAS latencies, 3rd byte */
74 unsigned char caslat_b4; /* 23 CAS latencies, 4th byte */
75 unsigned char taa_min; /* 24 Min CAS Latency Time */
76 unsigned char trcd_min; /* 25 Min RAS# to CAS# Delay Time */
77 unsigned char trp_min; /* 26 Min Row Precharge Delay Time */
78 unsigned char tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
79 unsigned char tras_min_lsb; /* 28 tRASmin, lsb */
80 unsigned char trc_min_lsb; /* 29 tRCmin, lsb */
81 unsigned char trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
82 unsigned char trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
83 unsigned char trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
84 unsigned char trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
85 unsigned char trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
86 unsigned char trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
87 unsigned char tfaw_msb; /* 36 Upper Nibble for tFAW */
88 unsigned char tfaw_min; /* 37 tFAW, lsb */
89 unsigned char trrds_min; /* 38 tRRD_Smin, MTB */
90 unsigned char trrdl_min; /* 39 tRRD_Lmin, MTB */
91 unsigned char tccdl_min; /* 40 tCCS_Lmin, MTB */
92 unsigned char res_41[60-41]; /* 41 Rserved */
93 unsigned char mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
94 unsigned char res_78[117-78]; /* 78~116, Reserved */
95 signed char fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */
96 signed char fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */
97 signed char fine_trrds_min; /* 119 Fine offset for tRRD_Smin */
98 signed char fine_trc_min; /* 120 Fine offset for tRCmin */
99 signed char fine_trp_min; /* 121 Fine offset for tRPmin */
100 signed char fine_trcd_min; /* 122 Fine offset for tRCDmin */
101 signed char fine_taa_min; /* 123 Fine offset for tAAmin */
102 signed char fine_tck_max; /* 124 Fine offset for tCKAVGmax */
103 signed char fine_tck_min; /* 125 Fine offset for tCKAVGmin */
105 unsigned char crc[2]; /* 126-127 SPD CRC */
108 union {
238 } mod_section;
240 unsigned char res_256[320-256]; /* 256~319 Reserved */
243 unsigned char mmid_lsb; /* 320 Module MfgID Code LSB */
244 unsigned char mmid_msb; /* 321 Module MfgID Code MSB */
245 unsigned char mloc; /* 322 Mfg Location */
246 unsigned char mdate[2]; /* 323~324 Mfg Date */
247 unsigned char sernum[4]; /* 325~328 Module Serial Number */
248 unsigned char mpart[20]; /* 329~348 Mfg's Module Part Number */
249 unsigned char mrev; /* 349 Module Revision Code */
250 unsigned char dmid_lsb; /* 350 DRAM MfgID Code LSB */
251 unsigned char dmid_msb; /* 351 DRAM MfgID Code MSB */
252 unsigned char stepping; /* 352 DRAM stepping */
253 unsigned char msd[29]; /* 353~381 Mfg's Specific Data */
254 unsigned char res_382[2]; /* 382~383 Reserved */