Lines Matching refs:U
16 #define CTX_GPREGS_OFFSET U(0x0)
17 #define CTX_GPREG_X0 U(0x0)
18 #define CTX_GPREG_X1 U(0x8)
19 #define CTX_GPREG_X2 U(0x10)
20 #define CTX_GPREG_X3 U(0x18)
21 #define CTX_GPREG_X4 U(0x20)
22 #define CTX_GPREG_X5 U(0x28)
23 #define CTX_GPREG_X6 U(0x30)
24 #define CTX_GPREG_X7 U(0x38)
25 #define CTX_GPREG_X8 U(0x40)
26 #define CTX_GPREG_X9 U(0x48)
27 #define CTX_GPREG_X10 U(0x50)
28 #define CTX_GPREG_X11 U(0x58)
29 #define CTX_GPREG_X12 U(0x60)
30 #define CTX_GPREG_X13 U(0x68)
31 #define CTX_GPREG_X14 U(0x70)
32 #define CTX_GPREG_X15 U(0x78)
33 #define CTX_GPREG_X16 U(0x80)
34 #define CTX_GPREG_X17 U(0x88)
35 #define CTX_GPREG_X18 U(0x90)
36 #define CTX_GPREG_X19 U(0x98)
37 #define CTX_GPREG_X20 U(0xa0)
38 #define CTX_GPREG_X21 U(0xa8)
39 #define CTX_GPREG_X22 U(0xb0)
40 #define CTX_GPREG_X23 U(0xb8)
41 #define CTX_GPREG_X24 U(0xc0)
42 #define CTX_GPREG_X25 U(0xc8)
43 #define CTX_GPREG_X26 U(0xd0)
44 #define CTX_GPREG_X27 U(0xd8)
45 #define CTX_GPREG_X28 U(0xe0)
46 #define CTX_GPREG_X29 U(0xe8)
47 #define CTX_GPREG_LR U(0xf0)
48 #define CTX_GPREG_SP_EL0 U(0xf8)
49 #define CTX_GPREGS_END U(0x100)
57 #define CTX_SCR_EL3 U(0x0)
58 #define CTX_ESR_EL3 U(0x8)
59 #define CTX_RUNTIME_SP U(0x10)
60 #define CTX_SPSR_EL3 U(0x18)
61 #define CTX_ELR_EL3 U(0x20)
62 #define CTX_PMCR_EL0 U(0x28)
63 #define CTX_IS_IN_EL3 U(0x30)
64 #define CTX_CPTR_EL3 U(0x38)
65 #define CTX_ZCR_EL3 U(0x40)
66 #define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */
75 #define CTX_SPSR_EL1 U(0x0)
76 #define CTX_ELR_EL1 U(0x8)
77 #define CTX_SCTLR_EL1 U(0x10)
78 #define CTX_TCR_EL1 U(0x18)
79 #define CTX_CPACR_EL1 U(0x20)
80 #define CTX_CSSELR_EL1 U(0x28)
81 #define CTX_SP_EL1 U(0x30)
82 #define CTX_ESR_EL1 U(0x38)
83 #define CTX_TTBR0_EL1 U(0x40)
84 #define CTX_TTBR1_EL1 U(0x48)
85 #define CTX_MAIR_EL1 U(0x50)
86 #define CTX_AMAIR_EL1 U(0x58)
87 #define CTX_ACTLR_EL1 U(0x60)
88 #define CTX_TPIDR_EL1 U(0x68)
89 #define CTX_TPIDR_EL0 U(0x70)
90 #define CTX_TPIDRRO_EL0 U(0x78)
91 #define CTX_PAR_EL1 U(0x80)
92 #define CTX_FAR_EL1 U(0x88)
93 #define CTX_AFSR0_EL1 U(0x90)
94 #define CTX_AFSR1_EL1 U(0x98)
95 #define CTX_CONTEXTIDR_EL1 U(0xa0)
96 #define CTX_VBAR_EL1 U(0xa8)
103 #define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */
104 #define CTX_SPSR_UND U(0xb8)
105 #define CTX_SPSR_IRQ U(0xc0)
106 #define CTX_SPSR_FIQ U(0xc8)
107 #define CTX_DACR32_EL2 U(0xd0)
108 #define CTX_IFSR32_EL2 U(0xd8)
109 #define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */
111 #define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */
119 #define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0))
120 #define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8))
121 #define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10))
122 #define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18))
123 #define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20))
124 #define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */
130 #define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0))
131 #define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8))
132 #define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10))
133 #define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18))
136 #define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20))
160 #define CTX_ACTLR_EL2 U(0x0)
161 #define CTX_AFSR0_EL2 U(0x8)
162 #define CTX_AFSR1_EL2 U(0x10)
163 #define CTX_AMAIR_EL2 U(0x18)
164 #define CTX_CNTHCTL_EL2 U(0x20)
165 #define CTX_CNTVOFF_EL2 U(0x28)
166 #define CTX_CPTR_EL2 U(0x30)
167 #define CTX_DBGVCR32_EL2 U(0x38)
168 #define CTX_ELR_EL2 U(0x40)
169 #define CTX_ESR_EL2 U(0x48)
170 #define CTX_FAR_EL2 U(0x50)
171 #define CTX_HACR_EL2 U(0x58)
172 #define CTX_HCR_EL2 U(0x60)
173 #define CTX_HPFAR_EL2 U(0x68)
174 #define CTX_HSTR_EL2 U(0x70)
175 #define CTX_ICC_SRE_EL2 U(0x78)
176 #define CTX_ICH_HCR_EL2 U(0x80)
177 #define CTX_ICH_VMCR_EL2 U(0x88)
178 #define CTX_MAIR_EL2 U(0x90)
179 #define CTX_MDCR_EL2 U(0x98)
180 #define CTX_PMSCR_EL2 U(0xa0)
181 #define CTX_SCTLR_EL2 U(0xa8)
182 #define CTX_SPSR_EL2 U(0xb0)
183 #define CTX_SP_EL2 U(0xb8)
184 #define CTX_TCR_EL2 U(0xc0)
185 #define CTX_TPIDR_EL2 U(0xc8)
186 #define CTX_TTBR0_EL2 U(0xd0)
187 #define CTX_VBAR_EL2 U(0xd8)
188 #define CTX_VMPIDR_EL2 U(0xe0)
189 #define CTX_VPIDR_EL2 U(0xe8)
190 #define CTX_VTCR_EL2 U(0xf0)
191 #define CTX_VTTBR_EL2 U(0xf8)
194 #define CTX_TFSR_EL2 U(0x100)
197 #define CTX_MPAM2_EL2 U(0x108)
198 #define CTX_MPAMHCR_EL2 U(0x110)
199 #define CTX_MPAMVPM0_EL2 U(0x118)
200 #define CTX_MPAMVPM1_EL2 U(0x120)
201 #define CTX_MPAMVPM2_EL2 U(0x128)
202 #define CTX_MPAMVPM3_EL2 U(0x130)
203 #define CTX_MPAMVPM4_EL2 U(0x138)
204 #define CTX_MPAMVPM5_EL2 U(0x140)
205 #define CTX_MPAMVPM6_EL2 U(0x148)
206 #define CTX_MPAMVPM7_EL2 U(0x150)
207 #define CTX_MPAMVPMV_EL2 U(0x158)
210 #define CTX_HDFGRTR_EL2 U(0x160)
211 #define CTX_HAFGRTR_EL2 U(0x168)
212 #define CTX_HDFGWTR_EL2 U(0x170)
213 #define CTX_HFGITR_EL2 U(0x178)
214 #define CTX_HFGRTR_EL2 U(0x180)
215 #define CTX_HFGWTR_EL2 U(0x188)
216 #define CTX_CNTPOFF_EL2 U(0x190)
219 #define CTX_CONTEXTIDR_EL2 U(0x198)
220 #define CTX_TTBR1_EL2 U(0x1a0)
221 #define CTX_VDISR_EL2 U(0x1a8)
222 #define CTX_VSESR_EL2 U(0x1b0)
223 #define CTX_VNCR_EL2 U(0x1b8)
224 #define CTX_TRFCR_EL2 U(0x1c0)
227 #define CTX_SCXTNUM_EL2 U(0x1c8)
230 #define CTX_HCRX_EL2 U(0x1d0)
233 #define CTX_EL2_SYSREGS_END U(0x1e0)
247 #define CTX_FP_Q0 U(0x0)
248 #define CTX_FP_Q1 U(0x10)
249 #define CTX_FP_Q2 U(0x20)
250 #define CTX_FP_Q3 U(0x30)
251 #define CTX_FP_Q4 U(0x40)
252 #define CTX_FP_Q5 U(0x50)
253 #define CTX_FP_Q6 U(0x60)
254 #define CTX_FP_Q7 U(0x70)
255 #define CTX_FP_Q8 U(0x80)
256 #define CTX_FP_Q9 U(0x90)
257 #define CTX_FP_Q10 U(0xa0)
258 #define CTX_FP_Q11 U(0xb0)
259 #define CTX_FP_Q12 U(0xc0)
260 #define CTX_FP_Q13 U(0xd0)
261 #define CTX_FP_Q14 U(0xe0)
262 #define CTX_FP_Q15 U(0xf0)
263 #define CTX_FP_Q16 U(0x100)
264 #define CTX_FP_Q17 U(0x110)
265 #define CTX_FP_Q18 U(0x120)
266 #define CTX_FP_Q19 U(0x130)
267 #define CTX_FP_Q20 U(0x140)
268 #define CTX_FP_Q21 U(0x150)
269 #define CTX_FP_Q22 U(0x160)
270 #define CTX_FP_Q23 U(0x170)
271 #define CTX_FP_Q24 U(0x180)
272 #define CTX_FP_Q25 U(0x190)
273 #define CTX_FP_Q26 U(0x1a0)
274 #define CTX_FP_Q27 U(0x1b0)
275 #define CTX_FP_Q28 U(0x1c0)
276 #define CTX_FP_Q29 U(0x1d0)
277 #define CTX_FP_Q30 U(0x1e0)
278 #define CTX_FP_Q31 U(0x1f0)
279 #define CTX_FP_FPSR U(0x200)
280 #define CTX_FP_FPCR U(0x208)
282 #define CTX_FP_FPEXC32_EL2 U(0x210)
283 #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */
285 #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */
288 #define CTX_FPREGS_END U(0)
295 #define CTX_CVE_2018_3639_DISABLE U(0)
296 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */
303 #define CTX_PACIAKEY_LO U(0x0)
304 #define CTX_PACIAKEY_HI U(0x8)
305 #define CTX_PACIBKEY_LO U(0x10)
306 #define CTX_PACIBKEY_HI U(0x18)
307 #define CTX_PACDAKEY_LO U(0x20)
308 #define CTX_PACDAKEY_HI U(0x28)
309 #define CTX_PACDBKEY_LO U(0x30)
310 #define CTX_PACDBKEY_HI U(0x38)
311 #define CTX_PACGAKEY_LO U(0x40)
312 #define CTX_PACGAKEY_HI U(0x48)
313 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */
315 #define CTX_PAUTH_REGS_END U(0)
328 #define DWORD_SHIFT U(3)