Lines Matching refs:ULL
71 #define ARM_DRTM_FUNC_MASK ULL(0x1)
74 #define ARM_DRTM_FEAT_ID_MASK ULL(0xff)
81 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK ULL(0xF)
82 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT ULL(0x1)
85 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK ULL(0x1)
86 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_NOT_SUPPORTED ULL(0x0)
87 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED ULL(0x1)
90 #define ARM_DRTM_TPM_FEATURES_FW_HASH_MASK ULL(0xFFFFFFFF)
91 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256 ULL(0xB)
92 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384 ULL(0xC)
93 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA512 ULL(0xD)
96 #define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK ULL(0xFFFFFFFF)
99 #define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK ULL(0xFFFFFFFF)
102 #define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xF)
105 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK ULL(0xFF)
106 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE ULL(0x1)
107 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_REGION ULL(0x2)
110 #define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK ULL(0xFF)
183 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK ULL(0x3)
184 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC ULL(0)
185 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WC ULL(1)
186 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WT ULL(2)
187 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WB ULL(3)
190 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK ULL(0x7)
191 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL ULL(0)
192 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR ULL(1)
193 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE ULL(2)
194 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NV ULL(3)
195 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_RSVD ULL(4)
198 #define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK ULL(0xFFFFFFFFFFFFF)