Lines Matching refs:PSCI_CPU_PWR_LVL
76 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),
212 assert(pwrlvl > PSCI_CPU_PWR_LVL); in psci_set_req_local_pwr_state()
213 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_set_req_local_pwr_state()
247 assert(pwrlvl > PSCI_CPU_PWR_LVL); in psci_get_req_local_pwr_states()
249 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_get_req_local_pwr_states()
312 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state(); in psci_get_target_local_pwr_states()
316 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_get_target_local_pwr_states()
338 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]); in psci_set_target_local_pwr_states()
367 for (i = PSCI_CPU_PWR_LVL + 1U; i <= end_lvl; i++) { in psci_get_parent_pwr_domain_nodes()
385 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_set_pwr_domains_to_run()
434 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_do_state_coordination()
506 for (i = (int) target_lvl; i >= (int) PSCI_CPU_PWR_LVL; i--) { in psci_validate_suspend_req()
551 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) { in psci_find_max_off_lvl()
567 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) { in psci_find_target_suspend_lvl()
588 for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) { in psci_acquire_pwr_domain_locks()
606 for (level = end_pwrlvl; level >= (PSCI_CPU_PWR_LVL + 1U); level--) { in psci_release_pwr_domain_locks()