Lines Matching refs:UL
20 #define AML_NSDRAM0_BASE UL(0x01000000)
21 #define AML_NSDRAM0_SIZE UL(0x0F000000)
23 #define AML_NSDRAM1_BASE UL(0x10000000)
24 #define AML_NSDRAM1_SIZE UL(0x00100000)
26 #define BL31_BASE UL(0x10100000)
27 #define BL31_SIZE UL(0x000C0000)
31 #define AML_SHARE_MEM_INPUT_BASE UL(0x100FE000)
32 #define AML_SHARE_MEM_OUTPUT_BASE UL(0x100FF000)
34 #define AML_SEC_DEVICE0_BASE UL(0xC0000000)
35 #define AML_SEC_DEVICE0_SIZE UL(0x09000000)
37 #define AML_SEC_DEVICE1_BASE UL(0xD0040000)
38 #define AML_SEC_DEVICE1_SIZE UL(0x00008000)
40 #define AML_TZRAM_BASE UL(0xD9000000)
41 #define AML_TZRAM_SIZE UL(0x00014000)
45 #define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
46 #define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
47 #define AML_PSCI_MAILBOX_BASE UL(0xD9013F00)
49 #define AML_TZROM_BASE UL(0xD9040000)
50 #define AML_TZROM_SIZE UL(0x00010000)
52 #define AML_SEC_DEVICE2_BASE UL(0xDA000000)
53 #define AML_SEC_DEVICE2_SIZE UL(0x00200000)
55 #define AML_SEC_DEVICE3_BASE UL(0xDA800000)
56 #define AML_SEC_DEVICE3_SIZE UL(0x00200000)
61 #define AML_GICD_BASE UL(0xC4301000)
62 #define AML_GICC_BASE UL(0xC4302000)
78 #define AML_UART0_AO_BASE UL(0xC81004C0)
85 #define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4)
87 #define AML_SYS_CPU_CFG7 UL(0xC8834664)
89 #define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C)
91 #define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404)
92 #define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
93 #define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
94 #define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428)
95 #define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
96 #define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
98 #define AML_SHA_DMA_BASE UL(0xC883E000)