Lines Matching refs:dram_info
18 struct dram_info dram_info; variable
131 dram_info.dram_type = ddrc_mstr & DDR_TYPE_MASK; in dram_info_init()
132 dram_info.num_rank = (ddrc_mstr >> 24) & ACTIVE_RANK_MASK; in dram_info_init()
136 dram_info.boot_fsp = current_fsp; in dram_info_init()
137 dram_info.current_fsp = current_fsp; in dram_info_init()
139 get_mr_values(dram_info.mr_table); in dram_info_init()
141 dram_info.timing_info = (struct dram_timing_info *)dram_timing_base; in dram_info_init()
145 if (!dram_info.timing_info->fsp_table[i]) { in dram_info_init()
150 dram_info.num_fsp = i; in dram_info_init()
153 if (dram_info.timing_info->fsp_table[idx] < 666) { in dram_info_init()
154 dram_info.bypass_mode = true; in dram_info_init()
156 dram_info.bypass_mode = false; in dram_info_init()
189 SMC_RET4(handle, dram_info.timing_info->fsp_table[0], in dram_dvfs_get_freq_info()
192 if (!dram_info.bypass_mode) { in dram_dvfs_get_freq_info()
193 SMC_RET4(handle, dram_info.timing_info->fsp_table[1], in dram_dvfs_get_freq_info()
196 SMC_RET4(handle, dram_info.timing_info->fsp_table[1], in dram_dvfs_get_freq_info()
199 if (!dram_info.bypass_mode) { in dram_dvfs_get_freq_info()
200 SMC_RET4(handle, dram_info.timing_info->fsp_table[2], in dram_dvfs_get_freq_info()
203 SMC_RET4(handle, dram_info.timing_info->fsp_table[2], in dram_dvfs_get_freq_info()
206 SMC_RET4(handle, dram_info.timing_info->fsp_table[3], in dram_dvfs_get_freq_info()
222 SMC_RET1(handle, dram_info.num_fsp); in dram_dvfs_handler()
247 if (dram_info.dram_type == DDRC_LPDDR4) { in dram_dvfs_handler()
248 lpddr4_swffc(&dram_info, dev_fsp, fsp_index); in dram_dvfs_handler()
250 } else if (dram_info.dram_type == DDRC_DDR4) { in dram_dvfs_handler()
251 ddr4_swffc(&dram_info, fsp_index); in dram_dvfs_handler()
254 dram_info.current_fsp = fsp_index; in dram_dvfs_handler()