Lines Matching refs:domain_id
112 void vpu_sft_reset_assert(uint32_t domain_id) in vpu_sft_reset_assert() argument
118 switch (domain_id) { in vpu_sft_reset_assert()
136 void vpu_sft_reset_deassert(uint32_t domain_id) in vpu_sft_reset_deassert() argument
142 switch (domain_id) { in vpu_sft_reset_deassert()
160 void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) in imx_gpc_pm_domain_enable() argument
162 if (domain_id >= MAX_DOMAINS) { in imx_gpc_pm_domain_enable()
166 struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; in imx_gpc_pm_domain_enable()
169 pu_domain_status |= (1 << domain_id); in imx_gpc_pm_domain_enable()
171 if (domain_id == VPU_G1 || domain_id == VPU_G2 || in imx_gpc_pm_domain_enable()
172 domain_id == VPU_H1) { in imx_gpc_pm_domain_enable()
173 vpu_sft_reset_assert(domain_id); in imx_gpc_pm_domain_enable()
177 if (domain_id != HSIOMIX) { in imx_gpc_pm_domain_enable()
190 if (domain_id == VPU_G1 || domain_id == VPU_G2 || in imx_gpc_pm_domain_enable()
191 domain_id == VPU_H1) { in imx_gpc_pm_domain_enable()
192 vpu_sft_reset_deassert(domain_id); in imx_gpc_pm_domain_enable()
197 if (domain_id == GPUMIX) { in imx_gpc_pm_domain_enable()
230 if (domain_id == VPUMIX) { in imx_gpc_pm_domain_enable()
240 if (domain_id == DISPMIX) { in imx_gpc_pm_domain_enable()
258 if (domain_id == GPUMIX) { in imx_gpc_pm_domain_enable()
276 pu_domain_status &= ~(1 << domain_id); in imx_gpc_pm_domain_enable()
278 if (domain_id == OTG1 || domain_id == OTG2) { in imx_gpc_pm_domain_enable()
283 if (domain_id == GPUMIX) { in imx_gpc_pm_domain_enable()
310 if (domain_id == GPUMIX) { in imx_gpc_pm_domain_enable()
333 if (domain_id != HSIOMIX) { in imx_gpc_pm_domain_enable()