Lines Matching refs:U
18 #define PLAT_PRIMARY_CPU U(0x0)
19 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
20 #define PLATFORM_CLUSTER_COUNT U(1)
21 #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
22 #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
29 #define PWR_DOMAIN_AT_MAX_LVL U(1)
30 #define PLAT_MAX_PWR_LVL U(2)
31 #define PLAT_MAX_OFF_STATE U(4)
32 #define PLAT_MAX_RET_STATE U(2)
34 #define PLAT_WAIT_RET_STATE U(1)
35 #define PLAT_STOP_OFF_STATE U(3)
37 #define PLAT_PRI_BITS U(3)
40 #define PLAT_SDEI_SGI_PRIVATE U(9)
43 #define BL2_BASE U(0x920000)
46 #define BL31_BASE U(0x900000)
47 #define IMX_FIP_BASE U(0x40310000)
48 #define IMX_FIP_SIZE U(0x000300000)
49 #define IMX_FIP_LIMIT U(FIP_BASE + FIP_SIZE)
52 #define IMX_FIP_MMC_BASE U(0x100000)
54 #define PLAT_IMX8MM_BOOT_MMC_BASE U(0x30B50000) /* SD */
56 #define BL31_BASE U(0x920000)
63 #define PLAT_NS_IMAGE_OFFSET U(0x40200000)
64 #define PLAT_NS_IMAGE_SIZE U(0x00200000)
69 #define PLAT_GICD_BASE U(0x38800000)
70 #define PLAT_GICR_BASE U(0x38880000)
78 #define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */
86 #define IMX_AIPSTZ1 U(0x301f0000)
87 #define IMX_AIPSTZ2 U(0x305f0000)
88 #define IMX_AIPSTZ3 U(0x309f0000)
89 #define IMX_AIPSTZ4 U(0x32df0000)
91 #define IMX_AIPS_BASE U(0x30000000)
92 #define IMX_AIPS_SIZE U(0x3000000)
93 #define IMX_GPV_BASE U(0x32000000)
94 #define IMX_GPV_SIZE U(0x800000)
95 #define IMX_AIPS1_BASE U(0x30200000)
96 #define IMX_AIPS4_BASE U(0x32c00000)
97 #define IMX_ANAMIX_BASE U(0x30360000)
98 #define IMX_CCM_BASE U(0x30380000)
99 #define IMX_SRC_BASE U(0x30390000)
100 #define IMX_GPC_BASE U(0x303a0000)
101 #define IMX_RDC_BASE U(0x303d0000)
102 #define IMX_CSU_BASE U(0x303e0000)
103 #define IMX_WDOG_BASE U(0x30280000)
104 #define IMX_SNVS_BASE U(0x30370000)
105 #define IMX_NOC_BASE U(0x32700000)
106 #define IMX_TZASC_BASE U(0x32F80000)
107 #define IMX_IOMUX_GPR_BASE U(0x30340000)
108 #define IMX_CAAM_BASE U(0x30900000)
109 #define IMX_DDRC_BASE U(0x3d400000)
110 #define IMX_DDRPHY_BASE U(0x3c000000)
111 #define IMX_DDR_IPS_BASE U(0x3d000000)
112 #define IMX_DDR_IPS_SIZE U(0x1800000)
113 #define IMX_VPUMIX_BASE U(0x38330000)
114 #define IMX_VPUMIX_SIZE U(0x100000)
115 #define IMX_ROM_BASE U(0x0)
116 #define IMX_ROM_SIZE U(0x40000)
117 #define IMX_NS_OCRAM_BASE U(0x900000)
118 #define IMX_NS_OCRAM_SIZE U(0x20000)
119 #define IMX_CAAM_RAM_BASE U(0x100000)
120 #define IMX_CAAM_RAM_SIZE U(0x10000)
121 #define IMX_DRAM_BASE U(0x40000000)
122 #define IMX_DRAM_SIZE U(0xc0000000)
124 #define GPV_BASE U(0x32000000)
125 #define GPV_SIZE U(0x800000)
127 #define IMX_GIC_SIZE U(0x200000)
129 #define WDOG_WSR U(0x2)
139 #define SRC_A53RCR0 U(0x4)
140 #define SRC_A53RCR1 U(0x8)
141 #define SRC_OTG1PHY_SCR U(0x20)
142 #define SRC_OTG2PHY_SCR U(0x24)
143 #define SRC_GPR1_OFFSET U(0x74)
144 #define SRC_GPR10_OFFSET U(0x98)
147 #define SNVS_LPCR U(0x38)
152 #define IOMUXC_GPR10 U(0x28)
156 #define ANAMIX_MISC_CTL U(0x124)
159 #define MAX_CSU_NUM U(64)
161 #define OCRAM_S_BASE U(0x00180000)
162 #define OCRAM_S_SIZE U(0x8000)