Lines Matching refs:pwr_domain
175 struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; in imx_gpc_pm_domain_enable() local
192 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
205 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
208 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
211 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) in imx_gpc_pm_domain_enable()
234 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
236 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
239 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) in imx_gpc_pm_domain_enable()
250 if (pwr_domain->always_on) { in imx_gpc_pm_domain_enable()
254 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
259 if (pwr_domain->need_sync) { in imx_gpc_pm_domain_enable()
261 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
264 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) in imx_gpc_pm_domain_enable()
269 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
289 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
292 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) in imx_gpc_pm_domain_enable()