Lines Matching refs:U
13 #define PLAT_PRIMARY_CPU U(0x0)
14 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
15 #define PLATFORM_CLUSTER_COUNT U(1)
16 #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
17 #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
24 #define PWR_DOMAIN_AT_MAX_LVL U(1)
25 #define PLAT_MAX_PWR_LVL U(2)
26 #define PLAT_MAX_OFF_STATE U(4)
27 #define PLAT_MAX_RET_STATE U(1)
30 #define PLAT_WAIT_OFF_STATE U(2)
31 #define PLAT_STOP_OFF_STATE U(3)
33 #define BL31_BASE U(0x910000)
34 #define BL31_LIMIT U(0x920000)
37 #define PLAT_NS_IMAGE_OFFSET U(0x40200000)
41 #define PLAT_GICD_BASE U(0x38800000)
42 #define PLAT_GICR_BASE U(0x38880000)
55 #define HAB_RVT_BASE U(0x00000880) /* HAB_RVT for i.MX8MQ */
57 #define IMX_BOOT_UART_BASE U(0x30860000)
63 #define IMX_AIPS_BASE U(0x30200000)
64 #define IMX_AIPS_SIZE U(0xC00000)
65 #define IMX_AIPS1_BASE U(0x30200000)
66 #define IMX_AIPS3_ARB_BASE U(0x30800000)
67 #define IMX_OCOTP_BASE U(0x30350000)
68 #define IMX_ANAMIX_BASE U(0x30360000)
69 #define IMX_CCM_BASE U(0x30380000)
70 #define IMX_SRC_BASE U(0x30390000)
71 #define IMX_GPC_BASE U(0x303a0000)
72 #define IMX_RDC_BASE U(0x303d0000)
73 #define IMX_CSU_BASE U(0x303e0000)
74 #define IMX_WDOG_BASE U(0x30280000)
75 #define IMX_SNVS_BASE U(0x30370000)
76 #define IMX_NOC_BASE U(0x32700000)
77 #define IMX_TZASC_BASE U(0x32F80000)
78 #define IMX_CAAM_BASE U(0x30900000)
79 #define IMX_IOMUX_GPR_BASE U(0x30340000)
80 #define IMX_DDRC_BASE U(0x3d400000)
81 #define IMX_DDRPHY_BASE U(0x3c000000)
82 #define IMX_DDR_IPS_BASE U(0x3d000000)
84 #define IMX_ROM_BASE U(0x00000000)
85 #define IMX_ROM_SIZE U(0x20000)
87 #define AIPSTZ1_BASE U(0x301f0000)
88 #define AIPSTZ2_BASE U(0x305f0000)
89 #define AIPSTZ3_BASE U(0x309f0000)
90 #define AIPSTZ4_BASE U(0x32df0000)
92 #define GPV_BASE U(0x32000000)
93 #define GPV_SIZE U(0x800000)
95 #define IMX_GIC_SIZE U(0x200000)
97 #define WDOG_WSR U(0x2)
107 #define SRC_A53RCR0 U(0x4)
108 #define SRC_A53RCR1 U(0x8)
109 #define SRC_OTG1PHY_SCR U(0x20)
110 #define SRC_OTG2PHY_SCR U(0x24)
111 #define SRC_GPR1_OFFSET U(0x74)
112 #define SRC_GPR10_OFFSET U(0x98)
115 #define SNVS_LPCR U(0x38)
121 #define IOMUXC_GPR10 U(0x28)
125 #define OCRAM_S_BASE U(0x00180000)
126 #define OCRAM_S_SIZE U(0x8000)