Lines Matching refs:reg_val
121 uint32_t reg_val; in plat_marvell_cpu_powerdown() local
127 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
128 reg_val |= 0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET; in plat_marvell_cpu_powerdown()
129 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); in plat_marvell_cpu_powerdown()
133 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
135 } while (!(reg_val & (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)) && in plat_marvell_cpu_powerdown()
139 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
140 reg_val &= ~PWRC_CPUN_CR_PWR_DN_RQ_MASK; in plat_marvell_cpu_powerdown()
141 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); in plat_marvell_cpu_powerdown()
146 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
148 } while (reg_val & PWRC_CPUN_CR_PWR_DN_RQ_MASK && exit_loop > 0); in plat_marvell_cpu_powerdown()
154 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
155 reg_val &= ~PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK; in plat_marvell_cpu_powerdown()
156 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); in plat_marvell_cpu_powerdown()
159 reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); in plat_marvell_cpu_powerdown()
160 reg_val &= ~CCU_B_PRCRN_CPUPORESET_STATIC_MASK; in plat_marvell_cpu_powerdown()
161 mmio_write_32(CCU_B_PRCRN_REG(cpu_id), reg_val); in plat_marvell_cpu_powerdown()
166 reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); in plat_marvell_cpu_powerdown()
168 } while (reg_val & CCU_B_PRCRN_CPUPORESET_STATIC_MASK && exit_loop > 0); in plat_marvell_cpu_powerdown()
229 uint32_t reg_val; in plat_marvell_cpu_powerup() local
241 reg_val = mmio_read_32(AP807_PWRC_LDO_CR0_REG); in plat_marvell_cpu_powerup()
242 reg_val &= ~(AP807_PWRC_LDO_CR0_MASK); in plat_marvell_cpu_powerup()
243 reg_val |= (AP807_PWRC_LDO_CR0_VAL << AP807_PWRC_LDO_CR0_OFFSET); in plat_marvell_cpu_powerup()
244 mmio_write_32(AP807_PWRC_LDO_CR0_REG, reg_val); in plat_marvell_cpu_powerup()
249 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerup()
250 reg_val |= 0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET; in plat_marvell_cpu_powerup()
251 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); in plat_marvell_cpu_powerup()
257 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerup()
258 reg_val |= 0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET; in plat_marvell_cpu_powerup()
259 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); in plat_marvell_cpu_powerup()
265 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerup()
267 } while (!(reg_val & (0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) && in plat_marvell_cpu_powerup()
274 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerup()
275 reg_val &= ~PWRC_CPUN_CR_ISO_ENABLE_MASK; in plat_marvell_cpu_powerup()
276 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); in plat_marvell_cpu_powerup()
281 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerup()
283 } while ((reg_val & (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)) && in plat_marvell_cpu_powerup()
287 reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); in plat_marvell_cpu_powerup()
288 reg_val |= 0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET; in plat_marvell_cpu_powerup()
289 mmio_write_32(CCU_B_PRCRN_REG(cpu_id), reg_val); in plat_marvell_cpu_powerup()
294 reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id)); in plat_marvell_cpu_powerup()
296 } while (!(reg_val & (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET)) && in plat_marvell_cpu_powerup()