Lines Matching refs:pstate
153 static void armv8_2_cpu_pwr_on_common(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_on_common() argument
169 static void armv8_2_cpu_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_dwn_common() argument
171 if ((pstate & MT_CPUPM_PWR_DOMAIN_PERCORE_DSU) != 0) { in armv8_2_cpu_pwr_dwn_common()
180 static void armv8_2_cpu_pwr_resume(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_resume() argument
182 armv8_2_cpu_pwr_on_common(state, pstate); in armv8_2_cpu_pwr_resume()
188 static void armv8_2_cpu_pwr_suspend(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_suspend() argument
193 armv8_2_cpu_pwr_dwn_common(state, pstate); in armv8_2_cpu_pwr_suspend()
196 static void armv8_2_cpu_pwr_on(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_on() argument
198 armv8_2_cpu_pwr_on_common(state, pstate); in armv8_2_cpu_pwr_on()
205 static void armv8_2_cpu_pwr_off(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_off() argument
210 armv8_2_cpu_pwr_dwn_common(state, pstate); in armv8_2_cpu_pwr_off()
233 unsigned int pstate = (MT_CPUPM_PWR_DOMAIN_CORE | MT_CPUPM_PWR_DOMAIN_PERCORE_DSU); in armv8_2_power_domain_on_finish() local
245 armv8_2_cpu_pwr_on(&pm_state, pstate); in armv8_2_power_domain_on_finish()
248 nb.pwr_domain = pstate; in armv8_2_power_domain_on_finish()
258 unsigned int pstate = (MT_CPUPM_PWR_DOMAIN_CORE | MT_CPUPM_PWR_DOMAIN_PERCORE_DSU); in armv8_2_power_domain_off() local
269 armv8_2_cpu_pwr_off(&pm_state, pstate); in armv8_2_power_domain_off()
272 nb.pwr_domain = pstate; in armv8_2_power_domain_off()
281 unsigned int pstate = 0; in armv8_2_power_domain_suspend() local
294 pstate = get_mediatek_pstate(CPUPM_PWR_OFF, in armv8_2_power_domain_suspend()
297 armv8_2_cpu_pwr_suspend(&pm_state, pstate); in armv8_2_power_domain_suspend()
299 if ((pstate & MT_CPUPM_PWR_DOMAIN_CLUSTER) != 0) { in armv8_2_power_domain_suspend()
303 if ((pstate & MT_CPUPM_PWR_DOMAIN_MCUSYS) != 0) { in armv8_2_power_domain_suspend()
308 nb.pwr_domain = pstate; in armv8_2_power_domain_suspend()
311 if (IS_AFFLV_PUBEVENT(pstate)) { in armv8_2_power_domain_suspend()
319 unsigned int pstate = 0; in armv8_2_power_domain_suspend_finish() local
332 pstate = get_mediatek_pstate(CPUPM_PWR_ON, in armv8_2_power_domain_suspend_finish()
335 if ((pstate & MT_CPUPM_PWR_DOMAIN_MCUSYS) != 0) { in armv8_2_power_domain_suspend_finish()
339 if ((pstate & MT_CPUPM_PWR_DOMAIN_CLUSTER) != 0) { in armv8_2_power_domain_suspend_finish()
343 armv8_2_cpu_pwr_resume(&pm_state, pstate); in armv8_2_power_domain_suspend_finish()
346 nb.pwr_domain = pstate; in armv8_2_power_domain_suspend_finish()
349 if (IS_AFFLV_PUBEVENT(pstate)) { in armv8_2_power_domain_suspend_finish()
358 unsigned int pstate = psci_get_pstate_type(power_state); in armv8_2_validate_power_state() local
367 if (mtk_cpu_pwr.ops->pwr_state_valid(aff_lvl, pstate) != 0) { in armv8_2_validate_power_state()
372 if (pstate == PSTATE_TYPE_STANDBY) { in armv8_2_validate_power_state()