Lines Matching refs:val
47 static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val) in tegra_fc_cc4_ctrl() argument
49 mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val); in tegra_fc_cc4_ctrl()
50 val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]); in tegra_fc_cc4_ctrl()
53 static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val) in tegra_fc_cpu_csr() argument
55 mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val); in tegra_fc_cpu_csr()
56 val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]); in tegra_fc_cpu_csr()
59 static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val) in tegra_fc_halt_cpu() argument
61 mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val); in tegra_fc_halt_cpu()
62 val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]); in tegra_fc_halt_cpu()
67 uint32_t val; in tegra_fc_prepare_suspend() local
69 val = FLOWCTRL_HALT_GIC_IRQ | FLOWCTRL_HALT_GIC_FIQ | in tegra_fc_prepare_suspend()
72 tegra_fc_halt_cpu(cpu_id, val); in tegra_fc_prepare_suspend()
74 val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | in tegra_fc_prepare_suspend()
76 tegra_fc_cpu_csr(cpu_id, val | csr); in tegra_fc_prepare_suspend()
137 uint32_t val; in tegra_fc_cluster_idle() local
148 val = FLOWCTRL_PG_CPU_NONCPU << FLOWCTRL_ENABLE_EXT; in tegra_fc_cluster_idle()
149 tegra_fc_prepare_suspend(cpu, val); in tegra_fc_cluster_idle()
158 uint32_t val; in tegra_fc_cluster_powerdn() local
169 val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; in tegra_fc_cluster_powerdn()
170 tegra_fc_prepare_suspend(cpu, val); in tegra_fc_cluster_powerdn()
179 uint32_t val; in tegra_fc_is_ccx_allowed() local
189 val = mmio_read_32(flowctrl_offset_cpu_csr[i]); in tegra_fc_is_ccx_allowed()
190 if ((val & FLOWCTRL_CSR_HALT_MASK) == 0U) { in tegra_fc_is_ccx_allowed()
204 uint32_t val; in tegra_fc_soc_powerdn() local
212 val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; in tegra_fc_soc_powerdn()
213 tegra_fc_prepare_suspend(cpu, val); in tegra_fc_soc_powerdn()
233 uint32_t val; in tegra_fc_cpu_off() local
239 val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | in tegra_fc_cpu_off()
241 tegra_fc_cpu_csr(cpu, val); in tegra_fc_cpu_off()
251 uint32_t val; in tegra_fc_lock_active_cluster() local
253 val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); in tegra_fc_lock_active_cluster()
254 val |= FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK; in tegra_fc_lock_active_cluster()
255 tegra_fc_write_32(FLOWCTRL_BPMP_CLUSTER_CONTROL, val); in tegra_fc_lock_active_cluster()
256 val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); in tegra_fc_lock_active_cluster()
307 uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL); in tegra_fc_enable_fiq_to_ccplex_routing() local
310 tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val | FLOWCTRL_FIQ2CCPLEX_ENABLE); in tegra_fc_enable_fiq_to_ccplex_routing()
318 uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL); in tegra_fc_disable_fiq_to_ccplex_routing() local
321 tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val & ~FLOWCTRL_FIQ2CCPLEX_ENABLE); in tegra_fc_disable_fiq_to_ccplex_routing()