Lines Matching refs:U
16 #define BL31_SIZE U(0x40000)
28 #define MCE_ARI_APERTURE_0_OFFSET U(0x0)
29 #define MCE_ARI_APERTURE_1_OFFSET U(0x10000)
30 #define MCE_ARI_APERTURE_2_OFFSET U(0x20000)
31 #define MCE_ARI_APERTURE_3_OFFSET U(0x30000)
32 #define MCE_ARI_APERTURE_4_OFFSET U(0x40000)
33 #define MCE_ARI_APERTURE_5_OFFSET U(0x50000)
37 #define MCE_ARI_APERTURES_MAX U(6)
40 #define MCE_ARI_APERTURE_SIZE U(0x10000)
45 #define MCE_CORE_ID_MAX U(8)
46 #define MCE_CORE_ID_MASK U(0x7)
53 #define PSTATE_ID_CORE_IDLE U(6)
54 #define PSTATE_ID_CORE_POWERDN U(7)
55 #define PSTATE_ID_SOC_POWERDN U(2)
63 #define PLAT_MAX_RET_STATE U(1)
64 #define PLAT_MAX_OFF_STATE U(8)
75 #define TEGRA186_TOP_WDT_IRQ U(49)
76 #define TEGRA186_AON_WDT_IRQ U(50)
78 #define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */
83 #define TEGRA186_CLK_SE U(103)
89 #define TEGRA_MISC_BASE U(0x00100000)
90 #define HARDWARE_REVISION_OFFSET U(0x4)
92 #define MISCREG_PFCFG U(0x200C)
97 #define TEGRA_TSA_BASE U(0x02400000)
102 #define TSA_CONFIG_STATIC0_CSW_SESWR U(0x4010)
103 #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET U(0x1100)
104 #define TSA_CONFIG_STATIC0_CSW_ETRW U(0x4038)
105 #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET U(0x1100)
106 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB U(0x5010)
107 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET U(0x1100)
108 #define TSA_CONFIG_STATIC0_CSW_AXISW U(0x7008)
109 #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET U(0x1100)
110 #define TSA_CONFIG_STATIC0_CSW_HDAW U(0xA008)
111 #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET U(0x100)
112 #define TSA_CONFIG_STATIC0_CSW_AONDMAW U(0xB018)
113 #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET U(0x1100)
114 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW U(0xD018)
115 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET U(0x1100)
116 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW U(0xD028)
117 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET U(0x1100)
118 #define TSA_CONFIG_STATIC0_CSW_APEDMAW U(0x12018)
119 #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET U(0x1100)
120 #define TSA_CONFIG_STATIC0_CSW_UFSHCW U(0x13008)
121 #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET U(0x1100)
122 #define TSA_CONFIG_STATIC0_CSW_AFIW U(0x13018)
123 #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET U(0x1100)
124 #define TSA_CONFIG_STATIC0_CSW_SATAW U(0x13028)
125 #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET U(0x1100)
126 #define TSA_CONFIG_STATIC0_CSW_EQOSW U(0x13038)
127 #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET U(0x1100)
128 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW U(0x15008)
129 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET U(0x1100)
130 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW U(0x15018)
131 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET U(0x1100)
144 #define TEGRA_MC_STREAMID_BASE U(0x02C00000)
145 #define TEGRA_MC_BASE U(0x02C10000)
148 #define MC_GSC_CONFIG_REGS_SIZE U(0x40)
149 #define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
151 #define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
152 #define MC_GSC_BASE_LO_SHIFT U(12)
153 #define MC_GSC_BASE_LO_MASK U(0xFFFFF)
154 #define MC_GSC_BASE_HI_SHIFT U(0)
155 #define MC_GSC_BASE_HI_MASK U(3)
156 #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31)
159 #define MC_SECURITY_CFG0_0 U(0x70)
160 #define MC_SECURITY_CFG1_0 U(0x74)
161 #define MC_SECURITY_CFG3_0 U(0x9BC)
163 #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20)
164 #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0)
165 #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0)
168 #define MC_VIDEO_PROTECT_BASE_HI U(0x978)
169 #define MC_VIDEO_PROTECT_BASE_LO U(0x648)
170 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64C)
171 #define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
172 #define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
178 #define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
179 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
180 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
181 #define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
182 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
185 #define MC_TZRAM_CARVEOUT_CFG U(0x2190)
186 #define MC_TZRAM_BASE_LO U(0x2194)
187 #define MC_TZRAM_BASE_HI U(0x2198)
188 #define MC_TZRAM_SIZE U(0x219C)
189 #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0)
190 #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4)
191 #define TZRAM_ALLOW_MPCORER (U(1) << 7)
192 #define TZRAM_ALLOW_MPCOREW (U(1) << 25)
197 #define TEGRA_UARTA_BASE U(0x03100000)
198 #define TEGRA_UARTB_BASE U(0x03110000)
199 #define TEGRA_UARTC_BASE U(0x0C280000)
200 #define TEGRA_UARTD_BASE U(0x03130000)
201 #define TEGRA_UARTE_BASE U(0x03140000)
202 #define TEGRA_UARTF_BASE U(0x03150000)
203 #define TEGRA_UARTG_BASE U(0x0C290000)
208 #define TEGRA_FUSE_BASE U(0x03820000)
209 #define OPT_SUBREVISION U(0x248)
210 #define SUBREVISION_MASK U(0xFF)
215 #define TEGRA_GICD_BASE U(0x03881000)
216 #define TEGRA_GICC_BASE U(0x03882000)
221 #define TEGRA_SE0_BASE U(0x03AC0000)
222 #define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
223 #define TEGRA_PKA1_BASE U(0x03AD0000)
224 #define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144)
225 #define TEGRA_RNG1_BASE U(0x03AE0000)
226 #define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
231 #define TEGRA_HSP_DBELL_BASE U(0x03C90000)
232 #define HSP_DBELL_1_ENABLE U(0x104)
233 #define HSP_DBELL_3_TRIGGER U(0x300)
234 #define HSP_DBELL_3_ENABLE U(0x304)
239 #define TEGRA_CAR_RESET_BASE U(0x05000000)
240 #define TEGRA_GPU_RESET_REG_OFFSET U(0x30)
241 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x34)
242 #define GPU_RESET_BIT (U(1) << 0)
243 #define GPU_SET_BIT (U(1) << 0)
244 #define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004)
245 #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008)
250 #define TEGRA_TMRUS_BASE U(0x0C2E0000)
251 #define TEGRA_TMRUS_SIZE U(0x1000)
256 #define TEGRA_PMC_BASE U(0x0C360000)
261 #define TEGRA_SCRATCH_BASE U(0x0C390000)
262 #define SECURE_SCRATCH_RSV0_HI U(0x654)
263 #define SECURE_SCRATCH_RSV1_LO U(0x658)
264 #define SECURE_SCRATCH_RSV1_HI U(0x65C)
265 #define SECURE_SCRATCH_RSV6 U(0x680)
266 #define SECURE_SCRATCH_RSV11_LO U(0x6A8)
267 #define SECURE_SCRATCH_RSV11_HI U(0x6AC)
268 #define SECURE_SCRATCH_RSV53_LO U(0x7F8)
269 #define SECURE_SCRATCH_RSV53_HI U(0x7FC)
270 #define SECURE_SCRATCH_RSV55_LO U(0x808)
271 #define SECURE_SCRATCH_RSV55_HI U(0x80C)
272 #define SECURE_SCRATCH_RSV63_LO U(0x848)
273 #define SECURE_SCRATCH_RSV63_HI U(0x84C)
274 #define SECURE_SCRATCH_RSV64_LO U(0x850)
275 #define SECURE_SCRATCH_RSV64_HI U(0x854)
276 #define SECURE_SCRATCH_RSV65_LO U(0x858)
277 #define SECURE_SCRATCH_RSV65_HI U(0x85c)
278 #define SECURE_SCRATCH_RSV66_LO U(0x860)
279 #define SECURE_SCRATCH_RSV66_HI U(0x864)
280 #define SECURE_SCRATCH_RSV68_LO U(0x870)
295 #define TEGRA_MMCRAB_BASE U(0x0E000000)
300 #define TEGRA_ARM_ACTMON_CTR_BASE U(0x0E060000)
301 #define TEGRA_DENVER_ACTMON_CTR_BASE U(0x0E070000)
306 #define TEGRA_SMMU0_BASE U(0x12000000)
311 #define TEGRA_TZRAM_BASE U(0x30000000)
312 #define TEGRA_TZRAM_SIZE U(0x40000)
317 #define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x3004C000)
318 #define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x3004D000)
319 #define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */