Lines Matching refs:U
27 .cs[0].bnds = U(0x03FFU),
28 .cs[1].bnds = U(0x03FF),
29 .cs[0].config = U(0x80050422),
30 .cs[1].config = U(0x80000422),
31 .cs[2].bnds = U(0x00),
32 .cs[3].bnds = U(0x00),
33 .cs[2].config = U(0x00),
34 .cs[3].config = U(0x00),
35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
43 .sdram_cfg[0] = U(0x65044008),
44 .sdram_cfg[1] = U(0x00401011),
45 .sdram_cfg[2] = U(0x00),
46 .sdram_mode[0] = U(0x06010C50),
47 .sdram_mode[1] = U(0x00280400),
48 .sdram_mode[2] = U(0x00),
49 .sdram_mode[3] = U(0x00),
50 .sdram_mode[4] = U(0x00),
51 .sdram_mode[5] = U(0x00),
52 .sdram_mode[6] = U(0x00),
53 .sdram_mode[7] = U(0x00),
54 .sdram_mode[8] = U(0x0500),
55 .sdram_mode[9] = U(0x10240000),
56 .sdram_mode[10] = U(0x00),
57 .sdram_mode[11] = U(0x00),
58 .sdram_mode[12] = U(0x00),
59 .sdram_mode[13] = U(0x00),
60 .sdram_mode[14] = U(0x00),
61 .sdram_mode[15] = U(0x00),
62 .md_cntl = U(0x00),
63 .interval = U(0x30C00000),
64 .data_init = U(0xDEADBEEF),
65 .init_addr = U(0x00),
66 .zq_cntl = U(0x8A090705),
67 .sdram_rcw[0] = U(0x00),
68 .sdram_rcw[1] = U(0x00),
69 .sdram_rcw[2] = U(0x00),
70 .sdram_rcw[3] = U(0x00),
71 .sdram_rcw[4] = U(0x00),
72 .sdram_rcw[5] = U(0x00),
73 .err_disable = U(0x00),
74 .err_int_en = U(0x00),
78 .cs[0].bnds = U(0x03FF),
79 .cs[1].bnds = U(0x03FF),
80 .cs[0].config = U(0x80050422),
81 .cs[1].config = U(0x80000422),
82 .cs[2].bnds = U(0x00),
83 .cs[3].bnds = U(0x00),
84 .cs[2].config = U(0x00),
85 .cs[3].config = U(0x00),
86 .timing_cfg[0] = U(0xFF990018),
87 .timing_cfg[1] = U(0x4F4A4844),
88 .timing_cfg[2] = U(0x0005601F),
89 .timing_cfg[3] = U(0x125F2100),
90 .timing_cfg[4] = U(0x02),
91 .timing_cfg[5] = U(0x07401400),
92 .timing_cfg[7] = U(0x3AA00000),
93 .timing_cfg[8] = U(0x09449B00),
94 .sdram_cfg[0] = U(0x65044008),
95 .sdram_cfg[1] = U(0x00401011),
96 .sdram_cfg[2] = U(0x00),
97 .sdram_mode[0] = U(0x06010C50),
98 .sdram_mode[1] = U(0x00280400),
99 .sdram_mode[2] = U(0x00),
100 .sdram_mode[3] = U(0x00),
101 .sdram_mode[4] = U(0x00),
102 .sdram_mode[5] = U(0x00),
103 .sdram_mode[6] = U(0x00),
104 .sdram_mode[7] = U(0x00),
105 .sdram_mode[8] = U(0x0500),
106 .sdram_mode[9] = U(0x10240000),
107 .sdram_mode[10] = U(0x00),
108 .sdram_mode[11] = U(0x00),
109 .sdram_mode[12] = U(0x00),
110 .sdram_mode[13] = U(0x00),
111 .sdram_mode[14] = U(0x00),
112 .sdram_mode[15] = U(0x00),
113 .md_cntl = U(0x00),
114 .interval = U(0x2C2E0000),
115 .data_init = U(0xDEADBEEF),
116 .init_addr = U(0x00),
117 .zq_cntl = U(0x8A090705),
118 .sdram_rcw[0] = U(0x00),
119 .sdram_rcw[1] = U(0x00),
120 .sdram_rcw[2] = U(0x00),
121 .sdram_rcw[3] = U(0x00),
122 .sdram_rcw[4] = U(0x00),
123 .sdram_rcw[5] = U(0x00),
124 .err_disable = U(0x00),
125 .err_int_en = U(0x00),
129 .cs[0].bnds = U(0x03FF),
130 .cs[1].bnds = U(0x03FF),
131 .cs[0].config = U(0x80050422),
132 .cs[1].config = U(0x80000422),
133 .cs[2].bnds = U(0x00),
134 .cs[3].bnds = U(0x00),
135 .cs[2].config = U(0x00),
136 .cs[3].config = U(0x00),
137 .timing_cfg[0] = U(0xFF880018),
138 .timing_cfg[1] = U(0x2A24F444),
139 .timing_cfg[2] = U(0x007141DC),
140 .timing_cfg[3] = U(0x125B2100),
141 .timing_cfg[4] = U(0x02),
142 .timing_cfg[5] = U(0x06401400),
143 .timing_cfg[7] = U(0x28800000),
144 .timing_cfg[8] = U(0x07338A00),
145 .sdram_cfg[0] = U(0x65044008),
146 .sdram_cfg[1] = U(0x00401011),
147 .sdram_cfg[2] = U(0x00),
148 .sdram_mode[0] = U(0x06010A70),
149 .sdram_mode[1] = U(0x00200400),
150 .sdram_mode[2] = U(0x00),
151 .sdram_mode[3] = U(0x00),
152 .sdram_mode[4] = U(0x00),
153 .sdram_mode[5] = U(0x00),
154 .sdram_mode[6] = U(0x00),
155 .sdram_mode[7] = U(0x00),
156 .sdram_mode[8] = U(0x0500),
157 .sdram_mode[9] = U(0x0C240000),
158 .sdram_mode[10] = U(0x00),
159 .sdram_mode[11] = U(0x00),
160 .sdram_mode[12] = U(0x00),
161 .sdram_mode[13] = U(0x00),
162 .sdram_mode[14] = U(0x00),
163 .sdram_mode[15] = U(0x00),
164 .md_cntl = U(0x00),
165 .interval = U(0x279C0000),
166 .data_init = U(0xDEADBEEF),
167 .init_addr = U(0x00),
168 .zq_cntl = U(0x8A090705),
169 .sdram_rcw[0] = U(0x00),
170 .sdram_rcw[1] = U(0x00),
171 .sdram_rcw[2] = U(0x00),
172 .sdram_rcw[3] = U(0x00),
173 .sdram_rcw[4] = U(0x00),
174 .sdram_rcw[5] = U(0x00),
175 .err_disable = U(0x00),
176 .err_int_en = U(0x00),
180 .rdimm = 0U,
207 .rank_density = U(0x200000000),
208 .capacity = U(0x400000000),
212 .die_density = U(0x5),
213 .rdimm = 0U,
217 .bank_addr_bits = 0U,
220 .burst_lengths_bitmask = U(0x0c),
223 .caslat_x = U(0x15FFFC00),
259 popts->vref_dimm = U(0x19); /* range 1, 83.4% */ in ddr_board_options()
266 popts->bstopre = 0U; /* auto precharge */ in ddr_board_options()
273 popts->trwt = U(0xf); in ddr_board_options()
274 popts->twrt = U(0x7); in ddr_board_options()
275 popts->trrt = U(0x7); in ddr_board_options()
276 popts->twwt = U(0x7); in ddr_board_options()
277 popts->vref_phy = U(0x6B); /* 83.6% */ in ddr_board_options()
283 popts->trwt = U(0x3); in ddr_board_options()
284 popts->twrt = U(0x3); in ddr_board_options()
285 popts->trrt = U(0x3); in ddr_board_options()
286 popts->twwt = U(0x3); in ddr_board_options()
287 popts->vref_phy = U(0x5D); /* 72% */ in ddr_board_options()