Lines Matching refs:PMU_BASE
103 val = mmio_read_32(PMU_BASE + PMU_BUS_IDE_REQ); in rk3288_pmu_bus_idle()
109 mmio_write_32(PMU_BASE + PMU_BUS_IDE_REQ, val); in rk3288_pmu_bus_idle()
111 while ((mmio_read_32(PMU_BASE + in rk3288_pmu_bus_idle()
116 mmio_read_32(PMU_BASE + PMU_BUS_IDE_ST), in rk3288_pmu_bus_idle()
170 mmio_write_32(PMU_BASE + PMU_WAKEUP_CFG1, in pmu_set_sleep_mode()
180 mmio_write_32(PMU_BASE + PMU_STABL_CNT, 32 * 30); in pmu_set_sleep_mode()
183 mmio_write_32(PMU_BASE + PMU_OSC_CNT, in pmu_set_sleep_mode()
193 mmio_write_32(PMU_BASE + PMU_WAKEUP_CFG1, in pmu_set_sleep_mode()
198 mmio_write_32(PMU_BASE + PMU_STABL_CNT, 24000 * 30); in pmu_set_sleep_mode()
201 mmio_write_32(PMU_BASE + PMU_OSC_CNT, 0); in pmu_set_sleep_mode()
204 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, mode_set); in pmu_set_sleep_mode()
205 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON1, mode_set1); in pmu_set_sleep_mode()
317 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, store_pmu_pwrmode_con); in rockchip_soc_sys_pwr_dm_resume()
342 store_pmu_pwrmode_con = mmio_read_32(PMU_BASE + PMU_PWRMODE_CON); in rockchip_soc_sys_pwr_dm_suspend()