Lines Matching refs:mmio_write_32
21 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass()
25 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass()
66 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
70 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2) + 1), in sgrf_ddr_rgn_config()
74 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
78 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_GATE); in secure_watchdog_gate()
89 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_UNGATE); in secure_watchdog_ungate()
94 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in sram_secure_timer_init()
96 mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT0, 0xffffffff); in sram_secure_timer_init()
97 mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT1, 0xffffffff); in sram_secure_timer_init()
100 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in sram_secure_timer_init()
106 mmio_write_32(CORE_AXI_BUS_BASE + CORE_AXI_SECURITY0, in secure_gic_init()
112 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in secure_timer_init()
114 mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT0, 0xffffffff); in secure_timer_init()
115 mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT1, 0xffffffff); in secure_timer_init()
118 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
127 mmio_write_32(TZPC_BASE + TZPC_R0SIZE, TZPC_SRAM_SECURE_4K(1)); in secure_sgrf_init()
132 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), SGRF_SOC_CON2_MST_NS); in secure_sgrf_init()
133 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_SOC_CON3_MST_NS); in secure_sgrf_init()
136 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), in secure_sgrf_init()
138 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON5_SECURE_WMSK); in secure_sgrf_init()
141 mmio_write_32(TZPC_BASE + TZPC_DECPROT1SET, 0xff); in secure_sgrf_init()
142 mmio_write_32(TZPC_BASE + TZPC_DECPROT2SET, 0xff); in secure_sgrf_init()
143 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), 0x3800); in secure_sgrf_init()
147 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in secure_sgrf_init()
150 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in secure_sgrf_init()
156 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); in secure_sgrf_init()
158 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); in secure_sgrf_init()