Lines Matching refs:cpu_id
36 static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) in get_cpus_pwr_domain_cfg_info() argument
40 pd_reg = mmio_read_32(PMU_BASE + PMU_PWRDN_CON) & BIT(cpu_id); in get_cpus_pwr_domain_cfg_info()
41 apm_reg = mmio_read_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id)) & in get_cpus_pwr_domain_cfg_info()
54 static int cpus_power_domain_on(uint32_t cpu_id) in cpus_power_domain_on() argument
58 cpu_pd = PD_CPU0 + cpu_id; in cpus_power_domain_on()
59 cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id); in cpus_power_domain_on()
63 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
68 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
75 WARN("%s: cpu%d is not in off,!\n", __func__, cpu_id); in cpus_power_domain_on()
79 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
86 static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) in cpus_power_domain_off() argument
90 cpu_pd = PD_CPU0 + cpu_id; in cpus_power_domain_off()
95 if (check_cpu_wfie(cpu_id, CKECK_WFEI_MSK)) in cpus_power_domain_off()
98 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
106 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
138 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); in rockchip_soc_cores_pwr_dm_on() local
140 assert(cpu_id < PLATFORM_CORE_COUNT); in rockchip_soc_cores_pwr_dm_on()
141 assert(cpuson_flags[cpu_id] == 0); in rockchip_soc_cores_pwr_dm_on()
142 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; in rockchip_soc_cores_pwr_dm_on()
143 cpuson_entry_point[cpu_id] = entrypoint; in rockchip_soc_cores_pwr_dm_on()
146 cpus_power_domain_on(cpu_id); in rockchip_soc_cores_pwr_dm_on()
153 uint32_t cpu_id = plat_my_core_pos(); in rockchip_soc_cores_pwr_dm_off() local
155 cpus_power_domain_off(cpu_id, core_pwr_wfi); in rockchip_soc_cores_pwr_dm_off()
162 uint32_t cpu_id = plat_my_core_pos(); in rockchip_soc_cores_pwr_dm_suspend() local
164 assert(cpu_id < PLATFORM_CORE_COUNT); in rockchip_soc_cores_pwr_dm_suspend()
165 assert(cpuson_flags[cpu_id] == 0); in rockchip_soc_cores_pwr_dm_suspend()
166 cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; in rockchip_soc_cores_pwr_dm_suspend()
167 cpuson_entry_point[cpu_id] = (uintptr_t)plat_get_sec_entrypoint(); in rockchip_soc_cores_pwr_dm_suspend()
170 cpus_power_domain_off(cpu_id, core_pwr_wfi_int); in rockchip_soc_cores_pwr_dm_suspend()
177 uint32_t cpu_id = plat_my_core_pos(); in rockchip_soc_cores_pwr_dm_on_finish() local
179 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_on_finish()
186 uint32_t cpu_id = plat_my_core_pos(); in rockchip_soc_cores_pwr_dm_resume() local
188 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_resume()