Lines Matching refs:CRU_BASE
43 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
90 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in sgrf_init()
93 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in sgrf_init()
99 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); in sgrf_init()
101 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); in sgrf_init()
127 plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in plls_suspend()
128 plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in plls_suspend()
129 plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in plls_suspend()
130 plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in plls_suspend()
132 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); in plls_suspend()
133 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS); in plls_suspend()
147 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), in plls_resume()
149 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), in plls_resume()
151 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), in plls_resume()
153 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), in plls_resume()
155 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), in plls_resume()
164 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); in soc_sleep_config()
168 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); in soc_sleep_config()
175 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), in pm_plls_resume()
177 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), in pm_plls_resume()
179 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), in pm_plls_resume()
181 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), in pm_plls_resume()
183 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), in pm_plls_resume()
191 mmio_write_32(CRU_BASE + PLL_CONS((GPLL_ID), 3), PLL_SLOW_BITS); in rockchip_soc_soft_reset()
192 mmio_write_32(CRU_BASE + PLL_CONS((CPLL_ID), 3), PLL_SLOW_BITS); in rockchip_soc_soft_reset()
193 mmio_write_32(CRU_BASE + PLL_CONS((NPLL_ID), 3), PLL_SLOW_BITS); in rockchip_soc_soft_reset()
194 mmio_write_32(CRU_BASE + PLL_CONS((ABPLL_ID), 3), PLL_SLOW_BITS); in rockchip_soc_soft_reset()
195 mmio_write_32(CRU_BASE + PLL_CONS((ALPLL_ID), 3), PLL_SLOW_BITS); in rockchip_soc_soft_reset()
197 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) | in rockchip_soc_soft_reset()
200 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); in rockchip_soc_soft_reset()
201 mmio_write_32(CRU_BASE + CRU_GLB_SRST_SND, 0xeca8); in rockchip_soc_soft_reset()