Lines Matching refs:CTL_REG
111 mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; in get_dram_drv_odt_val()
129 mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; in get_dram_drv_odt_val()
130 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; in get_dram_drv_odt_val()
157 mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; in get_dram_drv_odt_val()
158 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; in get_dram_drv_odt_val()
498 mmio_write_32(CTL_REG(i, 5), tmp); in gen_rk3399_ctl_params_f0()
500 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, in gen_rk3399_ctl_params_f0()
503 mmio_write_32(CTL_REG(i, 32), in gen_rk3399_ctl_params_f0()
507 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
511 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 + in gen_rk3399_ctl_params_f0()
513 mmio_write_32(CTL_REG(i, 32), in gen_rk3399_ctl_params_f0()
516 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
519 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1); in gen_rk3399_ctl_params_f0()
520 mmio_write_32(CTL_REG(i, 7), pdram_timing->tinit4); in gen_rk3399_ctl_params_f0()
521 mmio_write_32(CTL_REG(i, 32), in gen_rk3399_ctl_params_f0()
524 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
527 mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3); in gen_rk3399_ctl_params_f0()
528 mmio_write_32(CTL_REG(i, 8), pdram_timing->tinit5); in gen_rk3399_ctl_params_f0()
529 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), in gen_rk3399_ctl_params_f0()
531 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), in gen_rk3399_ctl_params_f0()
533 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); in gen_rk3399_ctl_params_f0()
534 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
537 mmio_write_32(CTL_REG(i, 27), in gen_rk3399_ctl_params_f0()
543 mmio_clrsetbits_32(CTL_REG(i, 31), 0xffu << 24, in gen_rk3399_ctl_params_f0()
545 mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) | in gen_rk3399_ctl_params_f0()
547 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, in gen_rk3399_ctl_params_f0()
549 mmio_clrsetbits_32(CTL_REG(i, 39), in gen_rk3399_ctl_params_f0()
553 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 16, in gen_rk3399_ctl_params_f0()
557 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp); in gen_rk3399_ctl_params_f0()
558 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp); in gen_rk3399_ctl_params_f0()
559 mmio_write_32(CTL_REG(i, 48), in gen_rk3399_ctl_params_f0()
562 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp); in gen_rk3399_ctl_params_f0()
563 mmio_clrsetbits_32(CTL_REG(i, 53), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
565 mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24, in gen_rk3399_ctl_params_f0()
567 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri); in gen_rk3399_ctl_params_f0()
568 mmio_write_32(CTL_REG(i, 56), in gen_rk3399_ctl_params_f0()
573 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr); in gen_rk3399_ctl_params_f0()
574 mmio_clrsetbits_32(CTL_REG(i, 62), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
577 mmio_write_32(CTL_REG(i, 63), in gen_rk3399_ctl_params_f0()
582 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, in gen_rk3399_ctl_params_f0()
585 mmio_clrsetbits_32(CTL_REG(i, 92), 0xffff << 8, in gen_rk3399_ctl_params_f0()
588 mmio_clrsetbits_32(CTL_REG(i, 108), 0x1 << 24, in gen_rk3399_ctl_params_f0()
590 mmio_clrsetbits_32(CTL_REG(i, 122), 0x3ff << 16, in gen_rk3399_ctl_params_f0()
592 mmio_write_32(CTL_REG(i, 123), (pdram_timing->tfc_long << 16) | in gen_rk3399_ctl_params_f0()
594 mmio_write_32(CTL_REG(i, 124), in gen_rk3399_ctl_params_f0()
598 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) | in gen_rk3399_ctl_params_f0()
600 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff, in gen_rk3399_ctl_params_f0()
602 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff, in gen_rk3399_ctl_params_f0()
604 mmio_clrsetbits_32(CTL_REG(i, 139), 0xffu << 24, in gen_rk3399_ctl_params_f0()
606 mmio_write_32(CTL_REG(i, 147), in gen_rk3399_ctl_params_f0()
609 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff, in gen_rk3399_ctl_params_f0()
611 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff, in gen_rk3399_ctl_params_f0()
613 mmio_clrsetbits_32(CTL_REG(i, 153), 0xffu << 24, in gen_rk3399_ctl_params_f0()
616 mmio_clrsetbits_32(CTL_REG(i, 140), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
618 mmio_clrsetbits_32(CTL_REG(i, 142), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
620 mmio_clrsetbits_32(CTL_REG(i, 145), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
622 mmio_clrsetbits_32(CTL_REG(i, 154), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
624 mmio_clrsetbits_32(CTL_REG(i, 156), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
626 mmio_clrsetbits_32(CTL_REG(i, 159), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
629 mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8, in gen_rk3399_ctl_params_f0()
631 mmio_write_32(CTL_REG(i, 180), (pdram_timing->tzqcs << 16) | in gen_rk3399_ctl_params_f0()
633 mmio_write_32(CTL_REG(i, 181), (pdram_timing->tzqlat << 16) | in gen_rk3399_ctl_params_f0()
635 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 8, in gen_rk3399_ctl_params_f0()
639 mmio_setbits_32(CTL_REG(i, 213), 1 << 16); in gen_rk3399_ctl_params_f0()
645 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16); in gen_rk3399_ctl_params_f0()
649 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp); in gen_rk3399_ctl_params_f0()
650 mmio_clrsetbits_32(CTL_REG(i, 221), (0x3 << 16) | (0xf << 8), in gen_rk3399_ctl_params_f0()
657 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp); in gen_rk3399_ctl_params_f0()
658 mmio_clrsetbits_32(CTL_REG(i, 82), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
661 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, in gen_rk3399_ctl_params_f0()
672 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 16, in gen_rk3399_ctl_params_f0()
686 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 8, in gen_rk3399_ctl_params_f0()
689 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 16, in gen_rk3399_ctl_params_f0()
694 mmio_clrsetbits_32(CTL_REG(i, 277), 0xffff, in gen_rk3399_ctl_params_f0()
697 mmio_clrsetbits_32(CTL_REG(i, 282), 0xffff, in gen_rk3399_ctl_params_f0()
700 mmio_write_32(CTL_REG(i, 283), 20 * pdram_timing->trefi); in gen_rk3399_ctl_params_f0()
707 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16); in gen_rk3399_ctl_params_f0()
711 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp); in gen_rk3399_ctl_params_f0()
725 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); in gen_rk3399_ctl_params_f0()
733 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp); in gen_rk3399_ctl_params_f0()
750 mmio_write_32(CTL_REG(i, 9), tmp); in gen_rk3399_ctl_params_f1()
751 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
753 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, in gen_rk3399_ctl_params_f1()
757 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
761 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1 + in gen_rk3399_ctl_params_f1()
763 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, in gen_rk3399_ctl_params_f1()
767 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
770 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1); in gen_rk3399_ctl_params_f1()
771 mmio_write_32(CTL_REG(i, 11), pdram_timing->tinit4); in gen_rk3399_ctl_params_f1()
772 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, in gen_rk3399_ctl_params_f1()
776 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
779 mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3); in gen_rk3399_ctl_params_f1()
780 mmio_write_32(CTL_REG(i, 12), pdram_timing->tinit5); in gen_rk3399_ctl_params_f1()
781 mmio_clrsetbits_32(CTL_REG(i, 24), (0x7f << 8), in gen_rk3399_ctl_params_f1()
783 mmio_clrsetbits_32(CTL_REG(i, 24), (0x1f << 16), in gen_rk3399_ctl_params_f1()
785 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f << 24, in gen_rk3399_ctl_params_f1()
787 mmio_clrsetbits_32(CTL_REG(i, 28), 0xffffff00, in gen_rk3399_ctl_params_f1()
791 mmio_clrsetbits_32(CTL_REG(i, 29), 0xffffff, in gen_rk3399_ctl_params_f1()
795 mmio_write_32(CTL_REG(i, 35), (pdram_timing->tcke << 24) | in gen_rk3399_ctl_params_f1()
797 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, in gen_rk3399_ctl_params_f1()
799 mmio_clrsetbits_32(CTL_REG(i, 39), (0xffu << 24), in gen_rk3399_ctl_params_f1()
801 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr); in gen_rk3399_ctl_params_f1()
802 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24, in gen_rk3399_ctl_params_f1()
806 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8); in gen_rk3399_ctl_params_f1()
807 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff << 8, in gen_rk3399_ctl_params_f1()
809 mmio_write_32(CTL_REG(i, 49), in gen_rk3399_ctl_params_f1()
812 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
814 mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff, in gen_rk3399_ctl_params_f1()
816 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff << 8, in gen_rk3399_ctl_params_f1()
818 mmio_write_32(CTL_REG(i, 57), (pdram_timing->tmrwckel << 24) | in gen_rk3399_ctl_params_f1()
822 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke); in gen_rk3399_ctl_params_f1()
823 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr); in gen_rk3399_ctl_params_f1()
824 mmio_clrsetbits_32(CTL_REG(i, 64), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
827 mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) | in gen_rk3399_ctl_params_f1()
831 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, in gen_rk3399_ctl_params_f1()
834 mmio_clrsetbits_32(CTL_REG(i, 92), (0xffu << 24), in gen_rk3399_ctl_params_f1()
836 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, in gen_rk3399_ctl_params_f1()
838 mmio_clrsetbits_32(CTL_REG(i, 108), (0x1 << 25), in gen_rk3399_ctl_params_f1()
840 mmio_write_32(CTL_REG(i, 125), in gen_rk3399_ctl_params_f1()
843 mmio_write_32(CTL_REG(i, 126), (pdram_timing->tckfspx << 24) | in gen_rk3399_ctl_params_f1()
846 mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff, in gen_rk3399_ctl_params_f1()
848 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
850 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) | in gen_rk3399_ctl_params_f1()
852 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
854 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11); in gen_rk3399_ctl_params_f1()
855 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
857 mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) | in gen_rk3399_ctl_params_f1()
859 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
861 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11); in gen_rk3399_ctl_params_f1()
863 mmio_clrsetbits_32(CTL_REG(i, 141), 0xffff, in gen_rk3399_ctl_params_f1()
865 mmio_clrsetbits_32(CTL_REG(i, 143), 0xffff, in gen_rk3399_ctl_params_f1()
867 mmio_clrsetbits_32(CTL_REG(i, 146), 0xffff, in gen_rk3399_ctl_params_f1()
869 mmio_clrsetbits_32(CTL_REG(i, 155), 0xffff, in gen_rk3399_ctl_params_f1()
871 mmio_clrsetbits_32(CTL_REG(i, 157), 0xffff, in gen_rk3399_ctl_params_f1()
873 mmio_clrsetbits_32(CTL_REG(i, 160), 0xffff, in gen_rk3399_ctl_params_f1()
876 mmio_write_32(CTL_REG(i, 182), in gen_rk3399_ctl_params_f1()
879 mmio_write_32(CTL_REG(i, 183), (pdram_timing->tzqcal << 16) | in gen_rk3399_ctl_params_f1()
881 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat); in gen_rk3399_ctl_params_f1()
882 mmio_clrsetbits_32(CTL_REG(i, 188), 0xfff, in gen_rk3399_ctl_params_f1()
884 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 16, in gen_rk3399_ctl_params_f1()
888 mmio_setbits_32(CTL_REG(i, 213), (1 << 24)); in gen_rk3399_ctl_params_f1()
894 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24)); in gen_rk3399_ctl_params_f1()
897 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp); in gen_rk3399_ctl_params_f1()
898 mmio_clrsetbits_32(CTL_REG(i, 221), 0xf << 24, in gen_rk3399_ctl_params_f1()
900 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck); in gen_rk3399_ctl_params_f1()
901 mmio_clrsetbits_32(CTL_REG(i, 291), 0xffff, in gen_rk3399_ctl_params_f1()
907 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff, in gen_rk3399_ctl_params_f1()
910 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
921 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 24, in gen_rk3399_ctl_params_f1()
936 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16, in gen_rk3399_ctl_params_f1()
939 mmio_clrsetbits_32(CTL_REG(i, 275), 0xffu << 24, in gen_rk3399_ctl_params_f1()
944 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
947 mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff, in gen_rk3399_ctl_params_f1()
950 mmio_write_32(CTL_REG(i, 290), 20 * pdram_timing->trefi); in gen_rk3399_ctl_params_f1()
957 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16); in gen_rk3399_ctl_params_f1()
961 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp); in gen_rk3399_ctl_params_f1()
976 mmio_clrsetbits_32(CTL_REG(i, 314), 0xffu << 24, tmp << 24); in gen_rk3399_ctl_params_f1()
984 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16); in gen_rk3399_ctl_params_f1()
998 mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); in gen_rk3399_enable_training()
999 mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); in gen_rk3399_enable_training()
1000 mmio_clrsetbits_32(CTL_REG(i, 70), 1 << 8, 1 << 8); in gen_rk3399_enable_training()
1009 mmio_clrbits_32(CTL_REG(i, 305), 1 << 16); in gen_rk3399_disable_training()
1010 mmio_clrbits_32(CTL_REG(i, 71), 1); in gen_rk3399_disable_training()
1011 mmio_clrbits_32(CTL_REG(i, 70), 1 << 8); in gen_rk3399_disable_training()
1762 mmio_clrbits_32(CTL_REG(i, 101), 0x7); in exit_low_power()
1764 if (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != in exit_low_power()
1766 while (mmio_read_32(CTL_REG(i, 200)) & 0x1) in exit_low_power()
1768 mmio_clrsetbits_32(CTL_REG(i, 93), 0xffu << 24, in exit_low_power()
1770 while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != in exit_low_power()
1795 mmio_setbits_32(CTL_REG(i, 101), val); in resume_low_power()
1815 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); in dram_low_power_config()
1846 trefi0 = ((mmio_read_32(CTL_REG(0, 48)) >> 16) & 0xffff) + 8; in dram_dfs_init()
1847 trefi1 = ((mmio_read_32(CTL_REG(0, 49)) >> 16) & 0xffff) + 8; in dram_dfs_init()
1852 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; in dram_dfs_init()
1958 mmio_write_32(CTL_REG(i, 102), pd_tmp); in dram_set_odt_pd()
1959 mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); in dram_set_odt_pd()
2097 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; in ddr_prepare_for_sys_resume()