Lines Matching refs:mmio_clrsetbits_32
500 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, in gen_rk3399_ctl_params_f0()
507 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
516 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
524 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
529 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), in gen_rk3399_ctl_params_f0()
531 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), in gen_rk3399_ctl_params_f0()
533 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); in gen_rk3399_ctl_params_f0()
534 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
543 mmio_clrsetbits_32(CTL_REG(i, 31), 0xffu << 24, in gen_rk3399_ctl_params_f0()
547 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, in gen_rk3399_ctl_params_f0()
549 mmio_clrsetbits_32(CTL_REG(i, 39), in gen_rk3399_ctl_params_f0()
553 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 16, in gen_rk3399_ctl_params_f0()
557 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp); in gen_rk3399_ctl_params_f0()
558 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp); in gen_rk3399_ctl_params_f0()
562 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp); in gen_rk3399_ctl_params_f0()
563 mmio_clrsetbits_32(CTL_REG(i, 53), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
565 mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24, in gen_rk3399_ctl_params_f0()
567 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri); in gen_rk3399_ctl_params_f0()
573 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr); in gen_rk3399_ctl_params_f0()
574 mmio_clrsetbits_32(CTL_REG(i, 62), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
582 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, in gen_rk3399_ctl_params_f0()
585 mmio_clrsetbits_32(CTL_REG(i, 92), 0xffff << 8, in gen_rk3399_ctl_params_f0()
588 mmio_clrsetbits_32(CTL_REG(i, 108), 0x1 << 24, in gen_rk3399_ctl_params_f0()
590 mmio_clrsetbits_32(CTL_REG(i, 122), 0x3ff << 16, in gen_rk3399_ctl_params_f0()
600 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff, in gen_rk3399_ctl_params_f0()
602 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff, in gen_rk3399_ctl_params_f0()
604 mmio_clrsetbits_32(CTL_REG(i, 139), 0xffu << 24, in gen_rk3399_ctl_params_f0()
609 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff, in gen_rk3399_ctl_params_f0()
611 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff, in gen_rk3399_ctl_params_f0()
613 mmio_clrsetbits_32(CTL_REG(i, 153), 0xffu << 24, in gen_rk3399_ctl_params_f0()
616 mmio_clrsetbits_32(CTL_REG(i, 140), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
618 mmio_clrsetbits_32(CTL_REG(i, 142), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
620 mmio_clrsetbits_32(CTL_REG(i, 145), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
622 mmio_clrsetbits_32(CTL_REG(i, 154), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
624 mmio_clrsetbits_32(CTL_REG(i, 156), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
626 mmio_clrsetbits_32(CTL_REG(i, 159), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
629 mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8, in gen_rk3399_ctl_params_f0()
635 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 8, in gen_rk3399_ctl_params_f0()
649 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp); in gen_rk3399_ctl_params_f0()
650 mmio_clrsetbits_32(CTL_REG(i, 221), (0x3 << 16) | (0xf << 8), in gen_rk3399_ctl_params_f0()
657 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp); in gen_rk3399_ctl_params_f0()
658 mmio_clrsetbits_32(CTL_REG(i, 82), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
661 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, in gen_rk3399_ctl_params_f0()
672 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 16, in gen_rk3399_ctl_params_f0()
686 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 8, in gen_rk3399_ctl_params_f0()
689 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 16, in gen_rk3399_ctl_params_f0()
694 mmio_clrsetbits_32(CTL_REG(i, 277), 0xffff, in gen_rk3399_ctl_params_f0()
697 mmio_clrsetbits_32(CTL_REG(i, 282), 0xffff, in gen_rk3399_ctl_params_f0()
707 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16); in gen_rk3399_ctl_params_f0()
711 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp); in gen_rk3399_ctl_params_f0()
725 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); in gen_rk3399_ctl_params_f0()
733 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp); in gen_rk3399_ctl_params_f0()
751 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
753 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, in gen_rk3399_ctl_params_f1()
757 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
763 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, in gen_rk3399_ctl_params_f1()
767 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
772 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, in gen_rk3399_ctl_params_f1()
776 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
781 mmio_clrsetbits_32(CTL_REG(i, 24), (0x7f << 8), in gen_rk3399_ctl_params_f1()
783 mmio_clrsetbits_32(CTL_REG(i, 24), (0x1f << 16), in gen_rk3399_ctl_params_f1()
785 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f << 24, in gen_rk3399_ctl_params_f1()
787 mmio_clrsetbits_32(CTL_REG(i, 28), 0xffffff00, in gen_rk3399_ctl_params_f1()
791 mmio_clrsetbits_32(CTL_REG(i, 29), 0xffffff, in gen_rk3399_ctl_params_f1()
797 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, in gen_rk3399_ctl_params_f1()
799 mmio_clrsetbits_32(CTL_REG(i, 39), (0xffu << 24), in gen_rk3399_ctl_params_f1()
801 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr); in gen_rk3399_ctl_params_f1()
802 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24, in gen_rk3399_ctl_params_f1()
806 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8); in gen_rk3399_ctl_params_f1()
807 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff << 8, in gen_rk3399_ctl_params_f1()
812 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
814 mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff, in gen_rk3399_ctl_params_f1()
816 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff << 8, in gen_rk3399_ctl_params_f1()
822 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke); in gen_rk3399_ctl_params_f1()
823 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr); in gen_rk3399_ctl_params_f1()
824 mmio_clrsetbits_32(CTL_REG(i, 64), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
831 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, in gen_rk3399_ctl_params_f1()
834 mmio_clrsetbits_32(CTL_REG(i, 92), (0xffu << 24), in gen_rk3399_ctl_params_f1()
836 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, in gen_rk3399_ctl_params_f1()
838 mmio_clrsetbits_32(CTL_REG(i, 108), (0x1 << 25), in gen_rk3399_ctl_params_f1()
846 mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff, in gen_rk3399_ctl_params_f1()
848 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
852 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
854 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11); in gen_rk3399_ctl_params_f1()
855 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
859 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
861 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11); in gen_rk3399_ctl_params_f1()
863 mmio_clrsetbits_32(CTL_REG(i, 141), 0xffff, in gen_rk3399_ctl_params_f1()
865 mmio_clrsetbits_32(CTL_REG(i, 143), 0xffff, in gen_rk3399_ctl_params_f1()
867 mmio_clrsetbits_32(CTL_REG(i, 146), 0xffff, in gen_rk3399_ctl_params_f1()
869 mmio_clrsetbits_32(CTL_REG(i, 155), 0xffff, in gen_rk3399_ctl_params_f1()
871 mmio_clrsetbits_32(CTL_REG(i, 157), 0xffff, in gen_rk3399_ctl_params_f1()
873 mmio_clrsetbits_32(CTL_REG(i, 160), 0xffff, in gen_rk3399_ctl_params_f1()
881 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat); in gen_rk3399_ctl_params_f1()
882 mmio_clrsetbits_32(CTL_REG(i, 188), 0xfff, in gen_rk3399_ctl_params_f1()
884 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 16, in gen_rk3399_ctl_params_f1()
897 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp); in gen_rk3399_ctl_params_f1()
898 mmio_clrsetbits_32(CTL_REG(i, 221), 0xf << 24, in gen_rk3399_ctl_params_f1()
900 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck); in gen_rk3399_ctl_params_f1()
901 mmio_clrsetbits_32(CTL_REG(i, 291), 0xffff, in gen_rk3399_ctl_params_f1()
907 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff, in gen_rk3399_ctl_params_f1()
910 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
921 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 24, in gen_rk3399_ctl_params_f1()
936 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16, in gen_rk3399_ctl_params_f1()
939 mmio_clrsetbits_32(CTL_REG(i, 275), 0xffu << 24, in gen_rk3399_ctl_params_f1()
944 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffffu << 16, in gen_rk3399_ctl_params_f1()
947 mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff, in gen_rk3399_ctl_params_f1()
957 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16); in gen_rk3399_ctl_params_f1()
961 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp); in gen_rk3399_ctl_params_f1()
976 mmio_clrsetbits_32(CTL_REG(i, 314), 0xffu << 24, tmp << 24); in gen_rk3399_ctl_params_f1()
984 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16); in gen_rk3399_ctl_params_f1()
998 mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); in gen_rk3399_enable_training()
999 mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); in gen_rk3399_enable_training()
1000 mmio_clrsetbits_32(CTL_REG(i, 70), 1 << 8, 1 << 8); in gen_rk3399_enable_training()
1037 mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp); in gen_rk3399_pi_params_f0()
1039 mmio_clrsetbits_32(PI_REG(i, 7), 0xffffu << 16, tmp << 16); in gen_rk3399_pi_params_f0()
1049 mmio_clrsetbits_32(PI_REG(i, 42), 0xff, tmp); in gen_rk3399_pi_params_f0()
1053 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f, tmp); in gen_rk3399_pi_params_f0()
1056 mmio_clrsetbits_32(PI_REG(i, 43), 0x3f << 8, in gen_rk3399_pi_params_f0()
1060 mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16, in gen_rk3399_pi_params_f0()
1063 mmio_clrsetbits_32(PI_REG(i, 46), 0xffffu << 16, in gen_rk3399_pi_params_f0()
1066 mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc); in gen_rk3399_pi_params_f0()
1070 mmio_clrsetbits_32(PI_REG(i, 66), 0xffu << 24, in gen_rk3399_pi_params_f0()
1085 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 16, tmp << 16); in gen_rk3399_pi_params_f0()
1102 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 8, tmp << 8); in gen_rk3399_pi_params_f0()
1105 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 16, tmp << 16); in gen_rk3399_pi_params_f0()
1108 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 16, tmp << 16); in gen_rk3399_pi_params_f0()
1117 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 16, tmp << 16); in gen_rk3399_pi_params_f0()
1123 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff << 16, tmp << 16); in gen_rk3399_pi_params_f0()
1125 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff, tmp + 18); in gen_rk3399_pi_params_f0()
1127 mmio_clrsetbits_32(PI_REG(i, 102), 0x1f << 8, in gen_rk3399_pi_params_f0()
1135 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 8, tmp << 8); in gen_rk3399_pi_params_f0()
1144 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 16, tmp << 16); in gen_rk3399_pi_params_f0()
1146 mmio_clrsetbits_32(PI_REG(i, 125), 0xffff << 8, in gen_rk3399_pi_params_f0()
1149 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]); in gen_rk3399_pi_params_f0()
1151 mmio_clrsetbits_32(PI_REG(i, 140), 0xffffu << 16, in gen_rk3399_pi_params_f0()
1154 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]); in gen_rk3399_pi_params_f0()
1156 mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]); in gen_rk3399_pi_params_f0()
1158 mmio_clrsetbits_32(PI_REG(i, 133), 0xffffu << 16, in gen_rk3399_pi_params_f0()
1161 mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]); in gen_rk3399_pi_params_f0()
1163 mmio_clrsetbits_32(PI_REG(i, 148), 0xffffu << 16, in gen_rk3399_pi_params_f0()
1166 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, in gen_rk3399_pi_params_f0()
1169 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 24, in gen_rk3399_pi_params_f0()
1172 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 16, in gen_rk3399_pi_params_f0()
1175 mmio_clrsetbits_32(PI_REG(i, 158), 0xff << 8, in gen_rk3399_pi_params_f0()
1178 mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp); in gen_rk3399_pi_params_f0()
1180 mmio_clrsetbits_32(PI_REG(i, 157), 0xffu << 24, in gen_rk3399_pi_params_f0()
1183 mmio_clrsetbits_32(PI_REG(i, 159), 0xffu << 24, in gen_rk3399_pi_params_f0()
1187 mmio_clrsetbits_32(PI_REG(i, 159), 0x1ffff, tmp); in gen_rk3399_pi_params_f0()
1189 mmio_clrsetbits_32(PI_REG(i, 160), 0x3f << 16, in gen_rk3399_pi_params_f0()
1192 mmio_clrsetbits_32(PI_REG(i, 160), 0xf, in gen_rk3399_pi_params_f0()
1195 mmio_clrsetbits_32(PI_REG(i, 187), 0xffff << 8, in gen_rk3399_pi_params_f0()
1198 mmio_clrsetbits_32(PI_REG(i, 188), 0xffffffff, in gen_rk3399_pi_params_f0()
1215 mmio_clrsetbits_32(PI_REG(i, 5), 0xffff, tmp); in gen_rk3399_pi_params_f1()
1217 mmio_clrsetbits_32(PI_REG(i, 12), 0xffff, tmp); in gen_rk3399_pi_params_f1()
1227 mmio_clrsetbits_32(PI_REG(i, 42), 0xff << 8, tmp << 8); in gen_rk3399_pi_params_f1()
1231 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f << 24, in gen_rk3399_pi_params_f1()
1235 mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); in gen_rk3399_pi_params_f1()
1237 mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, in gen_rk3399_pi_params_f1()
1240 mmio_clrsetbits_32(PI_REG(i, 47), 0xffffu << 16, in gen_rk3399_pi_params_f1()
1243 mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc); in gen_rk3399_pi_params_f1()
1247 mmio_clrsetbits_32(PI_REG(i, 67), 0xff << 8, tmp << 8); in gen_rk3399_pi_params_f1()
1261 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 24, tmp << 24); in gen_rk3399_pi_params_f1()
1278 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16); in gen_rk3399_pi_params_f1()
1281 mmio_clrsetbits_32(PI_REG(i, 89), 0xffu << 24, tmp << 24); in gen_rk3399_pi_params_f1()
1284 mmio_clrsetbits_32(PI_REG(i, 90), 0xffu << 24, tmp << 24); in gen_rk3399_pi_params_f1()
1293 mmio_clrsetbits_32(PI_REG(i, 91), 0xffu << 24, tmp << 24); in gen_rk3399_pi_params_f1()
1300 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff << 16, tmp << 16); in gen_rk3399_pi_params_f1()
1303 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff, tmp); in gen_rk3399_pi_params_f1()
1305 mmio_clrsetbits_32(PI_REG(i, 103), 0x1f, pdram_timing->tmrz); in gen_rk3399_pi_params_f1()
1313 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 16, in gen_rk3399_pi_params_f1()
1323 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 24, in gen_rk3399_pi_params_f1()
1326 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff, pdram_timing->mr[1]); in gen_rk3399_pi_params_f1()
1328 mmio_clrsetbits_32(PI_REG(i, 135), 0xffff << 8, in gen_rk3399_pi_params_f1()
1331 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff, pdram_timing->mr[1]); in gen_rk3399_pi_params_f1()
1333 mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8, in gen_rk3399_pi_params_f1()
1336 mmio_clrsetbits_32(PI_REG(i, 128), 0xffffu << 16, in gen_rk3399_pi_params_f1()
1339 mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]); in gen_rk3399_pi_params_f1()
1341 mmio_clrsetbits_32(PI_REG(i, 143), 0xffffu << 16, in gen_rk3399_pi_params_f1()
1344 mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]); in gen_rk3399_pi_params_f1()
1346 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff << 16, in gen_rk3399_pi_params_f1()
1349 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f << 8, in gen_rk3399_pi_params_f1()
1352 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr); in gen_rk3399_pi_params_f1()
1354 mmio_clrsetbits_32(PI_REG(i, 161), 0xffu << 24, in gen_rk3399_pi_params_f1()
1357 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16, in gen_rk3399_pi_params_f1()
1360 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8, in gen_rk3399_pi_params_f1()
1363 mmio_clrsetbits_32(PI_REG(i, 163), 0xffu << 24, in gen_rk3399_pi_params_f1()
1366 mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff, in gen_rk3399_pi_params_f1()
1369 mmio_clrsetbits_32(PI_REG(i, 164), 0x3f << 16, in gen_rk3399_pi_params_f1()
1372 mmio_clrsetbits_32(PI_REG(i, 164), 0xf, in gen_rk3399_pi_params_f1()
1375 mmio_clrsetbits_32(PI_REG(i, 189), 0xffff, in gen_rk3399_pi_params_f1()
1378 mmio_clrsetbits_32(PI_REG(i, 190), 0xffffffff, in gen_rk3399_pi_params_f1()
1400 mmio_clrsetbits_32(PHY_REG(i, 5), 0x7 << 16, drv_odt_val); in gen_rk3399_set_odt()
1401 mmio_clrsetbits_32(PHY_REG(i, 133), 0x7 << 16, drv_odt_val); in gen_rk3399_set_odt()
1402 mmio_clrsetbits_32(PHY_REG(i, 261), 0x7 << 16, drv_odt_val); in gen_rk3399_set_odt()
1403 mmio_clrsetbits_32(PHY_REG(i, 389), 0x7 << 16, drv_odt_val); in gen_rk3399_set_odt()
1405 mmio_clrsetbits_32(PHY_REG(i, 6), 0x7 << 24, drv_odt_val); in gen_rk3399_set_odt()
1406 mmio_clrsetbits_32(PHY_REG(i, 134), 0x7 << 24, drv_odt_val); in gen_rk3399_set_odt()
1407 mmio_clrsetbits_32(PHY_REG(i, 262), 0x7 << 24, drv_odt_val); in gen_rk3399_set_odt()
1408 mmio_clrsetbits_32(PHY_REG(i, 390), 0x7 << 24, drv_odt_val); in gen_rk3399_set_odt()
1439 mmio_clrsetbits_32(PHY_REG(ch, 1 + 128 * i), 0x7ff << 8, in gen_rk3399_phy_dll_bypass()
1442 mmio_clrsetbits_32(PHY_REG(ch, 11 + 128 * i), 0x3ff, in gen_rk3399_phy_dll_bypass()
1445 mmio_clrsetbits_32(PHY_REG(ch, 2 + 128 * i), 0x3ff, in gen_rk3399_phy_dll_bypass()
1447 mmio_clrsetbits_32(PHY_REG(ch, 78 + 128 * i), 0xf, in gen_rk3399_phy_dll_bypass()
1452 mmio_clrsetbits_32(PHY_REG(ch, 513 + 128 * i), in gen_rk3399_phy_dll_bypass()
1465 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), in gen_rk3399_phy_dll_bypass()
1472 mmio_clrsetbits_32(PHY_REG(ch, 78 + i * 128), in gen_rk3399_phy_dll_bypass()
1479 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), in gen_rk3399_phy_dll_bypass()
1489 mmio_clrsetbits_32(PHY_REG(ch, 86), 0xf << 8, sw_master_mode << 8); in gen_rk3399_phy_dll_bypass()
1490 mmio_clrsetbits_32(PHY_REG(ch, 214), 0xf << 8, sw_master_mode << 8); in gen_rk3399_phy_dll_bypass()
1491 mmio_clrsetbits_32(PHY_REG(ch, 342), 0xf << 8, sw_master_mode << 8); in gen_rk3399_phy_dll_bypass()
1492 mmio_clrsetbits_32(PHY_REG(ch, 470), 0xf << 8, sw_master_mode << 8); in gen_rk3399_phy_dll_bypass()
1495 mmio_clrsetbits_32(PHY_REG(ch, 547), 0xf << 16, sw_master_mode << 16); in gen_rk3399_phy_dll_bypass()
1496 mmio_clrsetbits_32(PHY_REG(ch, 675), 0xf << 16, sw_master_mode << 16); in gen_rk3399_phy_dll_bypass()
1497 mmio_clrsetbits_32(PHY_REG(ch, 803), 0xf << 16, sw_master_mode << 16); in gen_rk3399_phy_dll_bypass()
1517 mmio_clrsetbits_32(PHY_REG(i, 896), (0x3 << 8) | 1, fn << 8); in gen_rk3399_phy_params()
1531 mmio_clrsetbits_32(PHY_REG(i, 87), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1532 mmio_clrsetbits_32(PHY_REG(i, 215), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1533 mmio_clrsetbits_32(PHY_REG(i, 343), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1534 mmio_clrsetbits_32(PHY_REG(i, 471), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1541 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); in gen_rk3399_phy_params()
1542 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); in gen_rk3399_phy_params()
1549 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); in gen_rk3399_phy_params()
1550 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); in gen_rk3399_phy_params()
1562 mmio_clrsetbits_32(PHY_REG(i, 922), 0xf << 24, tmp << 24); in gen_rk3399_phy_params()
1569 mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); in gen_rk3399_phy_params()
1592 mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16); in gen_rk3399_phy_params()
1593 mmio_clrsetbits_32(PHY_REG(i, 205), 0x2ff << 16, tmp << 16); in gen_rk3399_phy_params()
1594 mmio_clrsetbits_32(PHY_REG(i, 333), 0x2ff << 16, tmp << 16); in gen_rk3399_phy_params()
1595 mmio_clrsetbits_32(PHY_REG(i, 461), 0x2ff << 16, tmp << 16); in gen_rk3399_phy_params()
1600 mmio_clrsetbits_32(PHY_REG(i, 10), 0xf, tmp); in gen_rk3399_phy_params()
1601 mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp); in gen_rk3399_phy_params()
1602 mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp); in gen_rk3399_phy_params()
1603 mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp); in gen_rk3399_phy_params()
1607 mmio_clrsetbits_32(PHY_REG(i, 80), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1608 mmio_clrsetbits_32(PHY_REG(i, 208), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1609 mmio_clrsetbits_32(PHY_REG(i, 336), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1610 mmio_clrsetbits_32(PHY_REG(i, 464), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1637 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1638 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1639 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1640 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 16, tmp << 16); in gen_rk3399_phy_params()
1643 mmio_clrsetbits_32(PHY_REG(i, 86), 0xf, tmp); in gen_rk3399_phy_params()
1644 mmio_clrsetbits_32(PHY_REG(i, 214), 0xf, tmp); in gen_rk3399_phy_params()
1645 mmio_clrsetbits_32(PHY_REG(i, 342), 0xf, tmp); in gen_rk3399_phy_params()
1646 mmio_clrsetbits_32(PHY_REG(i, 470), 0xf, tmp); in gen_rk3399_phy_params()
1658 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 8, tmp << 8); in gen_rk3399_phy_params()
1659 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 8, tmp << 8); in gen_rk3399_phy_params()
1660 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 8, tmp << 8); in gen_rk3399_phy_params()
1661 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 8, tmp << 8); in gen_rk3399_phy_params()
1664 mmio_clrsetbits_32(PHY_REG(i, 85), 0xf << 24, tmp << 24); in gen_rk3399_phy_params()
1665 mmio_clrsetbits_32(PHY_REG(i, 213), 0xf << 24, tmp << 24); in gen_rk3399_phy_params()
1666 mmio_clrsetbits_32(PHY_REG(i, 341), 0xf << 24, tmp << 24); in gen_rk3399_phy_params()
1667 mmio_clrsetbits_32(PHY_REG(i, 469), 0xf << 24, tmp << 24); in gen_rk3399_phy_params()
1768 mmio_clrsetbits_32(CTL_REG(i, 93), 0xffu << 24, in exit_low_power()
1815 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); in dram_low_power_config()
1896 mmio_clrsetbits_32(PHY_REG(0, 896), 0x3 << 8, in dram_dfs_init()
1959 mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); in dram_set_odt_pd()