Lines Matching refs:CTL_REG
181 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); in override_write_leveling_value()
476 mmio_setbits_32(CTL_REG(i, 276), 1 << 17); in dram_all_config()
501 sram_regcpy(CTL_REG(ch, 1), (uintptr_t)¶ms_ctl[1], in pctl_cfg()
503 mmio_write_32(CTL_REG(ch, 0), params_ctl[0]); in pctl_cfg()
510 mmio_clrsetbits_32(CTL_REG(ch, 68), PWRUP_SREFRESH_EXIT, in pctl_cfg()
518 mmio_setbits_32(CTL_REG(ch, 0), START); in pctl_cfg()
550 uint32_t fn = ((mmio_read_32(CTL_REG(0, 111)) >> 16) + 1) & 0x1; in dram_switch_to_next_index()
593 mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
594 mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
613 while (!(mmio_read_32(CTL_REG(0, 203)) & (1 << 3))) { in pctl_start()
622 mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
632 while (!(mmio_read_32(CTL_REG(1, 203)) & (1 << 3))) { in pctl_start()
641 mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
725 dram_regcpy((uintptr_t)¶ms_ctl[0], CTL_REG(0, 0), CTL_REG_NUM); in dmc_suspend()