Lines Matching refs:mmio_clrsetbits_32
152 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24, in set_cs_training_index()
173 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16, in override_write_leveling_value()
175 mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)), in override_write_leveling_value()
181 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); in override_write_leveling_value()
225 mmio_clrsetbits_32(PI_REG(ch, 100), 0x3 << 8, 0x2 << 8); in data_training()
228 mmio_clrsetbits_32(PI_REG(ch, 92), in data_training()
266 mmio_clrsetbits_32(PI_REG(ch, 60), 0x3 << 8, 0x2 << 8); in data_training()
268 mmio_clrsetbits_32(PI_REG(ch, 59), in data_training()
312 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 24, in data_training()
318 mmio_clrsetbits_32(PI_REG(ch, 74), in data_training()
360 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 16, in data_training()
363 mmio_clrsetbits_32(PI_REG(ch, 74), in data_training()
401 mmio_clrsetbits_32(PI_REG(ch, 124), 0x3 << 16, in data_training()
404 mmio_clrsetbits_32(PI_REG(ch, 121), in data_training()
486 mmio_clrsetbits_32(CRU_BASE + CRU_GLB_RST_CON, 0x3, 0x3); in dram_all_config()
510 mmio_clrsetbits_32(CTL_REG(ch, 68), PWRUP_SREFRESH_EXIT, in pctl_cfg()
514 mmio_clrsetbits_32(PHY_REG(ch, 957), 0x3 << 24, 1 << 24); in pctl_cfg()
571 mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1, in dram_switch_to_next_index()
604 mmio_clrsetbits_32(PHY_REG(0, 957), 0x3 << 24, in pctl_start()
607 mmio_clrsetbits_32(PHY_REG(1, 957), 0x3 << 24, in pctl_start()
626 mmio_clrsetbits_32(PHY_REG(0, 57 + 128 * byte), in pctl_start()
645 mmio_clrsetbits_32(PHY_REG(1, 57 + 128 * byte), in pctl_start()