Lines Matching refs:CRU_BASE
586 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
599 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
619 pll_st = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 3)) >> in clst_pwr_domain_resume()
843 clk_ddrc_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(3)); in sys_slp_config()
844 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1)); in sys_slp_config()
929 gpio_2_4_clk_gate = (mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)) >> in suspend_apio()
933 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in suspend_apio()
1053 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in resume_apio()
1283 store_cru[i / 4] = mmio_read_32(CRU_BASE + i); in cru_register_save()
1306 mmio_write_32(CRU_BASE + i, store_cru[i / 4]); in cru_register_restore()
1312 mmio_write_32(CRU_BASE + i, store_cru[i / 4]); in cru_register_restore()
1314 mmio_write_32(CRU_BASE + i, in cru_register_restore()
1446 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), in rockchip_soc_sys_pwr_dm_resume()