Lines Matching refs:PMU_BASE
83 mmio_clrsetbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, bus_id, bus_req); in pmu_bus_idle_req()
86 bus_state = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & bus_id; in pmu_bus_idle_req()
87 bus_ack = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK) & bus_id; in pmu_bus_idle_req()
97 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), in pmu_bus_idle_req()
100 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK), in pmu_bus_idle_req()
334 pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); in pmu_power_domains_suspend()
426 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); in rk3399_flush_l2_b()
433 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & in rk3399_flush_l2_b()
441 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); in rk3399_flush_l2_b()
448 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & in pmu_scu_b_pwrdn()
457 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); in pmu_scu_b_pwrdn()
459 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & in pmu_scu_b_pwrdn()
465 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); in pmu_scu_b_pwrdn()
471 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); in pmu_scu_b_pwrup()
506 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), in cpus_power_domain_on()
510 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 0); in cpus_power_domain_on()
521 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), in cpus_power_domain_on()
543 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), in cpus_power_domain_off()
554 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), in cpus_power_domain_off()
581 pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); in clst_pwr_domain_suspend()
591 pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); in clst_pwr_domain_suspend()
708 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), in rockchip_soc_cores_pwr_dm_on_finish()
728 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_resume()
794 mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(30)); in init_pmu_counts()
795 mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(30)); in init_pmu_counts()
798 mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_32K_CNT_MS(3)); in init_pmu_counts()
801 mmio_write_32(PMU_BASE + PMU_TIMEOUT_CNT, 0x5dc0); in init_pmu_counts()
806 mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(3)); in init_pmu_counts()
807 mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_24M_CNT_MS(1)); in init_pmu_counts()
808 mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_24M_CNT_MS(1)); in init_pmu_counts()
809 mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_24M_CNT_MS(1)); in init_pmu_counts()
820 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_MS(5)); in init_pmu_counts()
821 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_US(1)); in init_pmu_counts()
830 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_US(1)); in init_pmu_counts()
831 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_US(1)); in init_pmu_counts()
832 mmio_write_32(PMU_BASE + PMU_GPU_PWRDN_CNT, CYCL_24M_CNT_US(1)); in init_pmu_counts()
833 mmio_write_32(PMU_BASE + PMU_GPU_PWRUP_CNT, CYCL_24M_CNT_US(1)); in init_pmu_counts()
850 mmio_write_32(PMU_BASE + PMU_CCI500_CON, in sys_slp_config()
855 mmio_write_32(PMU_BASE + PMU_ADB400_CON, in sys_slp_config()
887 mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN)); in sys_slp_config()
888 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg); in sys_slp_config()
890 mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW); in sys_slp_config()
897 mmio_setbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); in set_hw_idle()
902 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); in clr_hw_idle()
1382 mmio_write_32(PMU_BASE + PMU_ADB400_CON, in rockchip_soc_sys_pwr_dm_suspend()
1390 while ((mmio_read_32(PMU_BASE + in rockchip_soc_sys_pwr_dm_suspend()
1395 mmio_read_32(PMU_BASE + PMU_ADB400_ST)); in rockchip_soc_sys_pwr_dm_suspend()
1400 mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN)); in rockchip_soc_sys_pwr_dm_suspend()
1456 mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff); in rockchip_soc_sys_pwr_dm_resume()
1457 mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00); in rockchip_soc_sys_pwr_dm_resume()
1463 mmio_write_32(PMU_BASE + PMU_CCI500_CON, in rockchip_soc_sys_pwr_dm_resume()
1468 mmio_clrbits_32(PMU_BASE + PMU_PWRDN_CON, in rockchip_soc_sys_pwr_dm_resume()
1471 mmio_write_32(PMU_BASE + PMU_ADB400_CON, in rockchip_soc_sys_pwr_dm_resume()
1483 while ((mmio_read_32(PMU_BASE + in rockchip_soc_sys_pwr_dm_resume()
1488 mmio_read_32(PMU_BASE + PMU_ADB400_ST)); in rockchip_soc_sys_pwr_dm_resume()
1612 mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE); in plat_rockchip_pmu_init()
1625 mmio_read_32(PMU_BASE + PMU_PWRDN_ST)); in plat_rockchip_pmu_init()