Lines Matching refs:x0
33 mrs x0, mpidr_el1
44 and x1, x0, #MPIDR_CPU_MASK
45 and x0, x0, #MPIDR_CLUSTER_MASK
46 add x0, x1, x0, LSR #6
58 mrs x0, mpidr_el1
59 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
60 cmp x0, #RPI_PRIMARY_CPU
80 lsl x0, x0, #3
82 add x0, x0, x2
89 str x1,[x0]
94 ldr x1, [x0]
99 mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT
100 ldr x1, [x0]
139 mov_imm x0, PLAT_RPI3_TM_HOLD_BASE
140 ldr x0, [x0]
141 cmp x0, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF
142 adr x0, plat_wait_for_warm_boot
143 csel x0, x0, xzr, eq
145 1: mov x0, #0
167 mov_imm x0, PLAT_RPI_MINI_UART_BASE
194 mov_imm x0, PLAT_RPI_MINI_UART_BASE
208 mrs x0, midr_el1
209 and x0, x0, #0xf0 /* Isolate low byte of part number */
236 mrs x0, CORTEX_A72_L2CTLR_EL1
238 orr x0, x0, x1
239 msr CORTEX_A72_L2CTLR_EL1, x0