Lines Matching refs:ULL
18 #define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
20 #define PLATFORM_STACK_SIZE ULL(0x1000)
67 #define SEC_ROM_BASE ULL(0x00000000)
68 #define SEC_ROM_SIZE ULL(0x00010000)
71 #define PLAT_RPI3_FIP_BASE ULL(0x00020000)
72 #define PLAT_RPI3_FIP_MAX_SIZE ULL(0x00010000)
75 #define SEC_SRAM_BASE ULL(0x00200000)
76 #define SEC_SRAM_SIZE ULL(0x00100000)
78 #define SEC_DRAM0_BASE ULL(0x00300000)
79 #define SEC_DRAM0_SIZE ULL(0x00100000)
82 #define NS_DRAM0_BASE ULL(0x00400000)
83 #define NS_DRAM0_SIZE ULL(0x00C00000)
85 #define SEC_ROM_BASE ULL(0x00000000)
86 #define SEC_ROM_SIZE ULL(0x00020000)
89 #define PLAT_RPI3_FIP_BASE ULL(0x00020000)
90 #define PLAT_RPI3_FIP_MAX_SIZE ULL(0x001E0000)
93 #define SEC_SRAM_BASE ULL(0x10000000)
94 #define SEC_SRAM_SIZE ULL(0x00100000)
96 #define SEC_DRAM0_BASE ULL(0x10100000)
97 #define SEC_DRAM0_SIZE ULL(0x00F00000)
100 #define NS_DRAM0_BASE ULL(0x11000000)
101 #define NS_DRAM0_SIZE ULL(0x01000000)
120 #define SHARED_RAM_SIZE ULL(0x00001000)
142 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
147 #define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)
154 #define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
155 #define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
156 #define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2)
167 #define PLAT_MAX_BL1_RW_SIZE ULL(0x12000)
180 #define PLAT_MAX_BL2_SIZE ULL(0x2C000)
191 #define PLAT_MAX_BL31_SIZE ULL(0x20000)
239 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
240 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
256 #define PLAT_RPI_UART_BAUDRATE ULL(115200)
261 #define SYS_COUNTER_FREQ_IN_TICKS ULL(19200000)