Lines Matching refs:U
35 #define STM32MP1_CHIP_ID U(0x501)
37 #define STM32MP135C_PART_NB U(0x05010000)
38 #define STM32MP135A_PART_NB U(0x05010001)
39 #define STM32MP133C_PART_NB U(0x050100C0)
40 #define STM32MP133A_PART_NB U(0x050100C1)
41 #define STM32MP131C_PART_NB U(0x050106C8)
42 #define STM32MP131A_PART_NB U(0x050106C9)
43 #define STM32MP135F_PART_NB U(0x05010800)
44 #define STM32MP135D_PART_NB U(0x05010801)
45 #define STM32MP133F_PART_NB U(0x050108C0)
46 #define STM32MP133D_PART_NB U(0x050108C1)
47 #define STM32MP131F_PART_NB U(0x05010EC8)
48 #define STM32MP131D_PART_NB U(0x05010EC9)
51 #define STM32MP1_CHIP_ID U(0x500)
53 #define STM32MP157C_PART_NB U(0x05000000)
54 #define STM32MP157A_PART_NB U(0x05000001)
55 #define STM32MP153C_PART_NB U(0x05000024)
56 #define STM32MP153A_PART_NB U(0x05000025)
57 #define STM32MP151C_PART_NB U(0x0500002E)
58 #define STM32MP151A_PART_NB U(0x0500002F)
59 #define STM32MP157F_PART_NB U(0x05000080)
60 #define STM32MP157D_PART_NB U(0x05000081)
61 #define STM32MP153F_PART_NB U(0x050000A4)
62 #define STM32MP153D_PART_NB U(0x050000A5)
63 #define STM32MP151F_PART_NB U(0x050000AE)
64 #define STM32MP151D_PART_NB U(0x050000AF)
67 #define STM32MP1_REV_B U(0x2000)
69 #define STM32MP1_REV_Y U(0x1003)
70 #define STM32MP1_REV_Z U(0x1001)
73 #define STM32MP1_REV_Z U(0x2001)
80 #define PKG_AA_LFBGA448 U(4)
81 #define PKG_AB_LFBGA354 U(3)
82 #define PKG_AC_TFBGA361 U(2)
83 #define PKG_AD_TFBGA257 U(1)
89 #define STM32MP_ROM_BASE U(0x00000000)
90 #define STM32MP_ROM_SIZE U(0x00020000)
91 #define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000)
94 #define STM32MP_SYSRAM_BASE U(0x2FFE0000)
95 #define STM32MP_SYSRAM_SIZE U(0x00020000)
96 #define SRAM1_BASE U(0x30000000)
97 #define SRAM1_SIZE U(0x00004000)
98 #define SRAM2_BASE U(0x30004000)
99 #define SRAM2_SIZE U(0x00002000)
100 #define SRAM3_BASE U(0x30006000)
101 #define SRAM3_SIZE U(0x00002000)
103 #define SRAMS_SIZE_2MB_ALIGNED U(0x00200000)
106 #define STM32MP_SYSRAM_BASE U(0x2FFC0000)
107 #define STM32MP_SYSRAM_SIZE U(0x00040000)
123 #define STM32MP_DDR_BASE U(0xC0000000)
124 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
138 #define STM32MP_HEADER_RESERVED_SIZE U(0x200)
145 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
147 #define STM32MP_HEADER_SIZE U(0x00000100)
149 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
162 #define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */
166 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
185 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
187 #define STM32MP_BL33_MAX_SIZE U(0x400000)
190 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
201 #define STM32MP1_DEVICE1_BASE U(0x40000000)
202 #define STM32MP1_DEVICE1_SIZE U(0x40000000)
204 #define STM32MP1_DEVICE2_BASE U(0x80000000)
205 #define STM32MP1_DEVICE2_SIZE U(0x40000000)
210 #define RCC_BASE U(0x50000000)
215 #define PWR_BASE U(0x50001000)
220 #define GPIOA_BASE U(0x50002000)
221 #define GPIOB_BASE U(0x50003000)
222 #define GPIOC_BASE U(0x50004000)
223 #define GPIOD_BASE U(0x50005000)
224 #define GPIOE_BASE U(0x50006000)
225 #define GPIOF_BASE U(0x50007000)
226 #define GPIOG_BASE U(0x50008000)
227 #define GPIOH_BASE U(0x50009000)
228 #define GPIOI_BASE U(0x5000A000)
230 #define GPIOJ_BASE U(0x5000B000)
231 #define GPIOK_BASE U(0x5000C000)
232 #define GPIOZ_BASE U(0x54004000)
234 #define GPIO_BANK_OFFSET U(0x1000)
237 #define GPIO_BANK_A U(0)
238 #define GPIO_BANK_B U(1)
239 #define GPIO_BANK_C U(2)
240 #define GPIO_BANK_D U(3)
241 #define GPIO_BANK_E U(4)
242 #define GPIO_BANK_F U(5)
243 #define GPIO_BANK_G U(6)
244 #define GPIO_BANK_H U(7)
245 #define GPIO_BANK_I U(8)
247 #define GPIO_BANK_J U(9)
248 #define GPIO_BANK_K U(10)
249 #define GPIO_BANK_Z U(25)
258 #define USART1_BASE U(0x4C000000)
259 #define USART2_BASE U(0x4C001000)
262 #define USART1_BASE U(0x5C000000)
263 #define USART2_BASE U(0x4000E000)
265 #define USART3_BASE U(0x4000F000)
266 #define UART4_BASE U(0x40010000)
267 #define UART5_BASE U(0x40011000)
268 #define USART6_BASE U(0x44003000)
269 #define UART7_BASE U(0x40018000)
270 #define UART8_BASE U(0x40019000)
304 #define STM32MP1_ETZPC_BASE U(0x5C007000)
307 #define STM32MP1_ETZPC_TZMA_ROM U(0)
308 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
402 #define STM32MP1_TZC_BASE U(0x5C006000)
415 #define STM32MP_SDMMC1_BASE U(0x58005000)
416 #define STM32MP_SDMMC2_BASE U(0x58007000)
417 #define STM32MP_SDMMC3_BASE U(0x48004000)
419 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
420 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
421 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
422 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
423 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
483 #define HW2_OTP_IWDG_HW_POS U(3)
484 #define HW2_OTP_IWDG_FZ_STOP_POS U(5)
485 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
497 #define NAND_PAGE_SIZE_2K U(0)
498 #define NAND_PAGE_SIZE_4K U(1)
499 #define NAND_PAGE_SIZE_8K U(2)
504 #define NAND_BLOCK_SIZE_64_PAGES U(0)
505 #define NAND_BLOCK_SIZE_128_PAGES U(1)
506 #define NAND_BLOCK_SIZE_256_PAGES U(2)
511 #define NAND_BLOCK_NB_UNIT U(256)
520 #define NAND_ECC_BIT_NB_UNSET U(0)
521 #define NAND_ECC_BIT_NB_1_BITS U(1)
522 #define NAND_ECC_BIT_NB_4_BITS U(2)
523 #define NAND_ECC_BIT_NB_8_BITS U(3)
524 #define NAND_ECC_ON_DIE U(4)
534 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
535 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
541 #define UID_WORD_NB U(3)
544 #define FWU_MAX_TRIAL_REBOOT U(3)
549 #define TAMP_BASE U(0x5C00A000)
550 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
551 #define TAMP_COUNTR U(0x40)
563 #define USB_OTG_BASE U(0x49000000)
568 #define DDRCTRL_BASE U(0x5A003000)
573 #define DDRPHYC_BASE U(0x5A004000)
578 #define IWDG_MAX_INSTANCE U(2)
579 #define IWDG1_INST U(0)
580 #define IWDG2_INST U(1)
582 #define IWDG1_BASE U(0x5C003000)
583 #define IWDG2_BASE U(0x5A002000)
588 #define BSEC_BASE U(0x5C005000)
590 #define CRYP_BASE U(0x54002000)
593 #define CRYP1_BASE U(0x54001000)
595 #define DBGMCU_BASE U(0x50081000)
597 #define HASH_BASE U(0x54003000)
600 #define HASH1_BASE U(0x54002000)
603 #define I2C3_BASE U(0x4C004000)
604 #define I2C4_BASE U(0x4C005000)
605 #define I2C5_BASE U(0x4C006000)
608 #define I2C4_BASE U(0x5C002000)
609 #define I2C6_BASE U(0x5c009000)
612 #define RNG_BASE U(0x54004000)
615 #define RNG1_BASE U(0x54003000)
617 #define RTC_BASE U(0x5c004000)
619 #define SPI4_BASE U(0x4C002000)
620 #define SPI5_BASE U(0x4C003000)
623 #define SPI6_BASE U(0x5c001000)
625 #define STGEN_BASE U(0x5c008000)
626 #define SYSCFG_BASE U(0x50020000)
631 #define SAES_BASE U(0x54005000)
636 #define PKA_BASE U(0x54006000)
642 #define PLAT_NB_RDEVS U(19)
644 #define PLAT_NB_FIXED_REGS U(2)