Lines Matching refs:r1
171 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
172 and r0, r1
186 and r1, r0, #MPIDR_CPU_MASK
188 add r0, r1, r0, LSR #6
209 ldr r1, =(RCC_BASE + DEBUG_UART_RST_REG)
211 str r2, [r1]
213 ldr r0, [r1]
216 str r2, [r1, #4] /* RSTCLR register */
218 ldr r0, [r1]
222 ldr r1, =(RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
223 ldr r2, [r1]
226 str r2, [r1]
227 ldr r1, =DEBUG_UART_TX_GPIO_BANK_ADDRESS
229 ldr r2, [r1, #GPIO_MODE_OFFSET]
232 str r2, [r1, #GPIO_MODE_OFFSET]
234 ldr r2, [r1, #GPIO_SPEED_OFFSET]
236 str r2, [r1, #GPIO_SPEED_OFFSET]
238 ldr r2, [r1, #GPIO_PUPD_OFFSET]
240 str r2, [r1, #GPIO_PUPD_OFFSET]
243 ldr r2, [r1, #GPIO_AFRH_OFFSET]
248 str r2, [r1, #GPIO_AFRH_OFFSET]
250 ldr r2, [r1, #GPIO_AFRL_OFFSET]
253 str r2, [r1, #GPIO_AFRL_OFFSET]
256 ldr r1, =(RCC_BASE + DEBUG_UART_TX_CLKSRC_REG)
258 str r2, [r1]
259 ldr r1, =(RCC_BASE + DEBUG_UART_TX_EN_REG)
260 ldr r2, [r1]
262 str r2, [r1]
265 ldr r1, =STM32MP_DEBUG_USART_CLK_FRQ
293 ldr r1, =STM32MP_DEBUG_USART_BASE