Lines Matching refs:ver
34 static unsigned int ver; in zynqmp_get_silicon_ver() local
36 if (!ver) { in zynqmp_get_silicon_ver()
37 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + in zynqmp_get_silicon_ver()
39 ver &= ZYNQMP_SILICON_VER_MASK; in zynqmp_get_silicon_ver()
40 ver >>= ZYNQMP_SILICON_VER_SHIFT; in zynqmp_get_silicon_ver()
43 return ver; in zynqmp_get_silicon_ver()
48 unsigned int ver = zynqmp_get_silicon_ver(); in zynqmp_get_uart_clk() local
50 if (ver == ZYNQMP_CSU_VERSION_QEMU) { in zynqmp_get_uart_clk()
60 uint32_t ver; member
70 .ver = 0x2c,
79 .ver = 0x2c,
89 .ver = 0x100,
95 .ver = 0x12c,
105 .ver = 0x100,
111 .ver = 0x12c,
121 .ver = 0x100,
127 .ver = 0x12c,
136 .ver = 0x2c,
145 .ver = 0x2c,
223 uint32_t id, ver, chipid[2]; in zynqmp_get_silicon_idcode_name() local
245 ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT; in zynqmp_get_silicon_idcode_name()
249 zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK)) { in zynqmp_get_silicon_idcode_name()
269 if ((ver & ZYNQMP_PL_STATUS_MASK) != 0U) { in zynqmp_get_silicon_idcode_name()
285 uint32_t ver; in zynqmp_get_rtl_ver() local
287 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); in zynqmp_get_rtl_ver()
288 ver &= ZYNQMP_RTL_VER_MASK; in zynqmp_get_rtl_ver()
289 ver >>= ZYNQMP_RTL_VER_SHIFT; in zynqmp_get_rtl_ver()
291 return ver; in zynqmp_get_rtl_ver()
315 uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); in zynqmp_get_ps_ver() local
317 ver &= ZYNQMP_PS_VER_MASK; in zynqmp_get_ps_ver()
318 ver >>= ZYNQMP_PS_VER_SHIFT; in zynqmp_get_ps_ver()
320 return ver + 1U; in zynqmp_get_ps_ver()
325 uint32_t ver = zynqmp_get_silicon_ver(); in zynqmp_print_platform_name() local
329 switch (ver) { in zynqmp_print_platform_name()
384 uint32_t ver = zynqmp_get_silicon_ver(); in plat_get_syscnt_freq2() local
386 if (ver == ZYNQMP_CSU_VERSION_QEMU) { in plat_get_syscnt_freq2()