booting.rst - OpenGrok cross reference for /linux-6.3-rc2/Documentation/arm64/booting.rst

Lines Matching refs:initialised
207   level where the kernel image will be entered must be initialised by
221     - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
226       - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
227       - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
234       - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
235       - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
244       ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
248       ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
256     - SCR_EL3.APK (bit 16) must be initialised to 0b1
257     - SCR_EL3.API (bit 17) must be initialised to 0b1
261     - HCR_EL2.APK (bit 40) must be initialised to 0b1
262     - HCR_EL2.API (bit 41) must be initialised to 0b1
268     - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
269     - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
270     - AMCNTENSET0_EL0 must be initialised to 0b1111
271     - AMCNTENSET1_EL0 must be initialised to a platform specific value
277     - AMCNTENSET0_EL0 must be initialised to 0b1111
278     - AMCNTENSET1_EL0 must be initialised to a platform specific value
286     - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
292     - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
298     - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
302     - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
308     - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
310     - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
315     - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
317     - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
319     - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
326     - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
328     - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
330     - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
335     - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
337     - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
339     - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
341     - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
344     - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
346     - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
348     - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
350     - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
356     - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
360     - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
366     - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
370     - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
376     - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
380     - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.