Lines Matching refs:L2
7 title: ARM L2 Cache Controller
15 implementations of the L2 cache controller have compatible programming
21 Note 1: The description in this document doesn't apply to integrated L2
23 integrated L2 controllers are assumed to be all preconfigured by
40 # offset needs to be added to the address before passing down to the L2
45 # maintenance operations on L1 are broadcasted to the L2 and L2
124 description: If present then L2 is forced to Write through mode
166 description: enable parity checking on the L2 cache (L220 or PL310).
170 description: disable parity checking on the L2 cache (L220 or PL310).
174 description: enable ECC protection on the L2 cache
178 description: disable the outer sync operation on the L2 cache.
200 L2 dynamic clock gating. Value: <0> (forcibly
207 description: L2 standby mode enable. Value <0> (forcibly disable),