Lines Matching refs:HDMI
7 title: Samsung Exynos SoC HDMI
34 Phandle to the HDMI DDC node.
38 Provides voltage source for DCC lines available on HDMI connector. When
40 HPD (hot plug detect) line, what causes HDMI block to stay turned off.
53 description: Phandle to the HDMI PHY node.
81 VDD 1.0V HDMI TX.
85 VDD 1.8V HDMI OSC.
89 VDD 1.0V HDMI PLL.
116 - description: Gate of HDMI IP APB bus.
117 - description: Gate of HDMI-PHY IP APB bus.
118 - description: Gate of HDMI TMDS clock.
119 - description: Gate of HDMI pixel clock.
120 - description: TMDS clock generated by HDMI-PHY.
122 respectively if HDMI-PHY is off and operational.
123 - description: Pixel clock generated by HDMI-PHY.
125 respectively if HDMI-PHY is off and operational.
127 clocks in case HDMI-PHY is not operational.
128 - description: Gate of HDMI SPDIF clock.
147 - description: Gate of HDMI IP bus clock.
148 - description: Gate of HDMI special clock.
150 of HDMI clock mux.
151 - description: HDMI PHY clock output, one of two possible inputs of
152 HDMI clock mux.