Lines Matching refs:topckgen
143 <&topckgen CLK_TOP_UNIVPLL_D2>,
144 <&topckgen CLK_TOP_CCI400_SEL>,
145 <&topckgen CLK_TOP_VDEC_SEL>,
146 <&topckgen CLK_TOP_VCODECPLL>,
148 <&topckgen CLK_TOP_VENC_LT_SEL>,
149 <&topckgen CLK_TOP_VCODECPLL_370P5>;
158 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
159 <&topckgen CLK_TOP_CCI400_SEL>,
160 <&topckgen CLK_TOP_VDEC_SEL>,
163 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
164 <&topckgen CLK_TOP_UNIVPLL_D2>,
165 <&topckgen CLK_TOP_VCODECPLL>;