Lines Matching refs:smi
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
25 SMI generation 1 to transform the smi clock into emi clock domain, but that is
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
34 - mediatek,mt6779-smi-common
35 - mediatek,mt6795-smi-common
36 - mediatek,mt8167-smi-common
37 - mediatek,mt8173-smi-common
38 - mediatek,mt8183-smi-common
39 - mediatek,mt8186-smi-common
40 - mediatek,mt8188-smi-common-vdo
41 - mediatek,mt8188-smi-common-vpp
42 - mediatek,mt8192-smi-common
43 - mediatek,mt8195-smi-common-vdo
44 - mediatek,mt8195-smi-common-vpp
45 - mediatek,mt8195-smi-sub-common
49 - const: mediatek,mt7623-smi-common
50 - const: mediatek,mt2701-smi-common
60 apb and smi are mandatory. the async is only for generation 1 smi HW.
66 - description: smi is the clock for transfer data and command.
67 - description: Either asynchronous clock to help transform the smi clock
75 mediatek,smi:
77 description: a phandle to the smi-common node above. Only for sub-common.
92 - mediatek,mt2701-smi-common
101 - const: smi
109 - mediatek,mt8195-smi-sub-common
112 - mediatek,smi
120 - const: smi
124 mediatek,smi: false
130 - mediatek,mt6779-smi-common
131 - mediatek,mt8183-smi-common
132 - mediatek,mt8186-smi-common
133 - mediatek,mt8192-smi-common
134 - mediatek,mt8195-smi-common-vdo
135 - mediatek,mt8195-smi-common-vpp
145 - const: smi
153 - mediatek,mt2712-smi-common
154 - mediatek,mt6795-smi-common
155 - mediatek,mt8167-smi-common
156 - mediatek,mt8173-smi-common
166 - const: smi
175 smi_common: smi@14022000 {
176 compatible = "mediatek,mt8173-smi-common";
181 clock-names = "apb", "smi";