Lines Matching refs:Value
41 description: Value of the delay in the input path for SD high-speed timing
47 description: Value of the delay in the input path for legacy timing
53 description: Value of the delay in the input path for SD UHS SDR12 timing
59 description: Value of the delay in the input path for SD UHS SDR25 timing
65 description: Value of the delay in the input path for SD UHS SDR50 timing
71 description: Value of the delay in the input path for SD UHS DDR50 timing
77 description: Value of the delay in the input path for MMC high-speed timing
83 description: Value of the delay in the input path for eMMC high-speed DDR timing
95 Value of the delay introduced on the sdclk output for all modes except
103 Value of the delay introduced on the sdclk output for HS200, HS400 and
111 Value of the delay introduced on the dat_strobe input used in