Lines Matching refs:loads
178 perceived by the loads made by another CPU in the same order as the stores were
247 (*) Overlapping loads and stores within a particular CPU will appear to be
275 (*) It _must_not_ be assumed that independent loads and stores will be issued
369 deferral and combination of memory operations; speculative loads; speculative
388 to have any effect on loads.
401 case where two loads are performed such that the second depends on the
408 loads only; it is not required to have any effect on stores, independent
409 loads or overlapping loads.
417 that touched by the load will be perceptible to any loads issued after
434 dependency barriers. Nowadays, APIs for marking loads from shared
445 A read barrier is a partial ordering on loads only; it is not required to
462 A general memory barrier is a partial ordering over both loads and stores.
714 load from 'a' with other loads from 'a'. Without the WRITE_ONCE(),
889 (*) Control dependencies can order prior loads against later stores.
891 Not prior loads against later loads, nor prior stores against
894 later loads, smp_mb().
983 match the loads after the read barrier or the address-dependency barrier, and
1037 dependent loads. Consider the following sequence of events:
1119 subsequent loads +-------+ | |
1123 And thirdly, a read barrier acts as a partial order on loads. Consider the
1209 Even though the two loads of A both occur after the load of B, they may both
1269 Many CPUs speculate with loads: that is they see that they will need to load an
1271 other loads, and so do the load in advance - even though they haven't actually
1389 CPU 2 executes its load before its store, and CPU 3 loads from Y before
1390 it loads from X. The question is then "Can CPU 3's load from X return 0?"
1494 subsequent loads in all cases. This means that cpu3() can see cpu0()'s
1553 (*) The compiler is within its rights to reorder loads and stores
1555 rights to reorder loads to the same variable. This means that
1570 (*) The compiler is within its rights to merge successive loads from
1766 The compiler can also invent loads. These are usually less
1769 invented loads.
1809 loads followed by a pair of 32-bit stores. This would result in
1845 to issue the loads in the correct order (eg. `a[b]` would have to load
2228 If a wakeup does occur, one (at least) of the two loads must see 1. If, on
2229 the other hand, a wakeup does not occur, both loads might see 0.
2234 the two loads would be guaranteed to see 1.
2258 order multiple stores before the wake-up with respect to loads of those stored
2739 their own loads and stores as if they had happened in program order.
2807 (*) loads are more likely to need to be completed immediately to permit
2811 (*) loads may be done speculatively, and the result discarded should it prove
2814 (*) loads may be done speculatively, leading to the result having been fetched
2820 (*) loads and stores may be combined to improve performance when talking to
2866 where a given CPU might reorder successive loads to the same location.