Lines Matching refs:memory
5 Provide infrastructure and helpers to integrate non-conventional memory (device
6 memory like GPU on board memory) into regular kernel path, with the cornerstone
7 of this being specialized struct page for such memory (see sections 5 to 7 of
18 related to using device specific memory allocators. In the second section, I
22 fifth section deals with how device memory is represented inside the kernel.
28 Problems of using a device specific memory allocator
31 Devices with a large amount of on board memory (several gigabytes) like GPUs
32 have historically managed their memory through dedicated driver specific APIs.
33 This creates a disconnect between memory allocated and managed by a device
34 driver and regular application memory (private anonymous, shared memory, or
35 regular file backed memory). From here on I will refer to this aspect as split
37 i.e., one in which any application memory region can be used by a device
40 Split address space happens because devices can only access memory allocated
41 through a device specific API. This implies that all memory objects in a program
46 to copy objects between generically allocated memory (malloc, mmap private, mmap
47 share) and memory allocated through the device driver API (this still ends up
58 might have to duplicate its input data set using the device specific memory
60 various memory copies.
62 Duplicating each library API to accept as input or output memory allocated by
73 I/O bus, device memory characteristics
77 buses only allow basic memory access from device to main memory; even cache
78 coherency is often optional. Access to device memory from a CPU is even more
81 If we only consider the PCIE bus, then a device can access main memory (often
83 a limited set of atomic operations from the device on main memory. This is worse
85 memory and cannot perform atomic operations on it. Thus device memory cannot
86 be considered the same as regular memory from the kernel point of view.
89 and 16 lanes). This is 33 times less than the fastest GPU memory (1 TBytes/s).
90 The final limitation is latency. Access to main memory from the device has an
91 order of magnitude higher latency than when the device accesses its own memory.
100 access any memory but we must also permit any memory to be migrated to device
101 memory while the device is using it (blocking CPU access while it happens).
109 address points to the same physical memory for any valid main memory address in
121 The second mechanism HMM provides is a new kind of ZONE_DEVICE memory that
122 allows allocating a struct page for each page of device memory. Those pages
124 main memory to device memory using existing migration mechanisms and everything
128 memory for the device memory and second to perform migration. Policy decisions
132 back to main memory. For example, when a page backing a given CPU address A is
133 migrated from a main memory page to a device page, then any CPU access to
134 address A triggers a page fault and initiates a migration back to main memory.
138 leverages device memory by migrating the part of the data set that is actively being
253 Represent and manage device memory from core kernel point of view
256 Several different designs were tried to support device memory. The first one
257 used a device specific data structure to keep information about migrated memory
259 addresses that were backed by device memory. It turns out that this ended up
261 paths to be updated to understand this new kind of memory.
263 Most kernel code paths never try to access the memory behind a page
265 directly using struct page for device memory which left most kernel code paths
269 Migration to and from device memory
272 Because the CPU cannot access device memory directly, the device driver must
278 Before migrating pages to device private memory, special device private
281 a page that has been migrated to device private memory.
305 memory (see Documentation/mm/page_migration.rst) but the steps are split
319 ``MIGRATE_VMA_SELECT_SYSTEM`` will only migrate system memory and
321 device private memory. If the latter flag is set, the ``args->pgmap_owner``
325 system memory and device private memory.
341 This lets the driver allocate device private memory and clear it instead
342 of copying a page of zeros. Valid PTE entries to system memory or
344 from the LRU (if system memory since device private pages are not on
358 system memory page, locks the page with ``lock_page()``, and fills in the
364 invalidate device private MMU mappings and copy device private memory
365 to system memory or another device private page. The core Linux kernel
371 destination or clear the destination device private memory if the pointer
372 is ``NULL`` meaning the source page was not populated in system memory.
406 Exclusive access memory
410 atomic access to system memory. To support atomic operations to a shared virtual
411 memory page such a device needs access to that page which is exclusive of any
413 can be used to make a memory range inaccessible from userspace.
426 For now, device memory is accounted as any regular page in rss counters (either
428 file backed page, or shmem if device page is used for shared memory). This is a
430 memory without knowing about it, running unimpacted.
433 device memory and not a lot of regular system memory and thus not freeing much
434 system memory. We want to gather more real world experience on how applications
435 and system react under memory pressure in the presence of device memory before
436 deciding to account device memory differently.
439 Same decision was made for memory cgroup. Device memory pages are accounted
440 against same memory cgroup a regular page would be accounted to. This does
441 simplify migration to and from device memory. This also means that migration
442 back from device memory to regular memory cannot fail because it would
443 go above memory cgroup limit. We might revisit this choice latter on once we
444 get more experience in how device memory is used and its impact on memory
448 Note that device memory can never be pinned by a device driver nor through GUP
449 and thus such memory is always free upon process exit. Or when last reference
450 is dropped in case of shared memory or file backed memory.