Lines Matching refs:write_aux_reg
258 write_aux_reg(aux_tag, paddr); in __cache_line_loop_v3()
268 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v3()
272 write_aux_reg(aux_tag, paddr); in __cache_line_loop_v3()
276 write_aux_reg(aux_cmd, vaddr); in __cache_line_loop_v3()
323 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v4()
325 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v4()
329 write_aux_reg(aux_cmd, paddr); in __cache_line_loop_v4()
369 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v4()
371 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32); in __cache_line_loop_v4()
375 write_aux_reg(e, paddr + sz); /* ENDR is exclusive */ in __cache_line_loop_v4()
376 write_aux_reg(s, paddr); in __cache_line_loop_v4()
409 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH); in __before_dc_op()
433 write_aux_reg(ctl, val); in __before_dc_op()
451 write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH); in __after_dc_op()
472 write_aux_reg(aux, 0x1); in __dc_entire_op()
482 write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS); in __dc_disable()
489 write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS); in __dc_enable()
529 write_aux_reg(ARC_REG_IC_IVIC, 1); in __ic_entire_inv()
620 write_aux_reg(ARC_REG_SLC_CTRL, ctrl); in slc_op_rgn()
629 write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end)); in slc_op_rgn()
631 write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end)); in slc_op_rgn()
634 write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr)); in slc_op_rgn()
636 write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr)); in slc_op_rgn()
674 write_aux_reg(ARC_REG_SLC_CTRL, ctrl); in slc_op_line()
684 write_aux_reg(cmd, paddr); in slc_op_line()
710 write_aux_reg(r, ctrl); in slc_entire_op()
713 write_aux_reg(ARC_REG_SLC_INVALIDATE, 0x1); in slc_entire_op()
715 write_aux_reg(ARC_REG_SLC_FLUSH, 0x1); in slc_entire_op()
729 write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS); in arc_slc_disable()
736 write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS); in arc_slc_enable()
1111 write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, order_base_2(mem_sz >> 10) - 2); in arc_ioc_setup()
1119 write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ioc_base >> 12); in arc_ioc_setup()
1120 write_aux_reg(ARC_REG_IO_COH_PARTIAL, ARC_IO_COH_PARTIAL_BIT); in arc_ioc_setup()
1121 write_aux_reg(ARC_REG_IO_COH_ENABLE, ARC_IO_COH_ENABLE_BIT); in arc_ioc_setup()
1238 write_aux_reg(ARC_REG_IC_PTAG_HI, 0); in arc_cache_init()
1241 write_aux_reg(ARC_REG_DC_PTAG_HI, 0); in arc_cache_init()
1244 write_aux_reg(ARC_REG_SLC_RGN_END1, 0); in arc_cache_init()
1245 write_aux_reg(ARC_REG_SLC_RGN_START1, 0); in arc_cache_init()