Lines Matching refs:write_aux_reg
29 write_aux_reg(ARC_REG_TLBPD1, 0); in __tlb_entry_erase()
32 write_aux_reg(ARC_REG_TLBPD1HI, 0); in __tlb_entry_erase()
34 write_aux_reg(ARC_REG_TLBPD0, 0); in __tlb_entry_erase()
35 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); in __tlb_entry_erase()
40 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB); in utlb_invalidate()
49 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); in tlb_entry_lkup()
51 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe); in tlb_entry_lkup()
91 write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex); in tlb_entry_insert()
94 write_aux_reg(ARC_REG_TLBPD1, pd1); in tlb_entry_insert()
101 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); in tlb_entry_insert()
108 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT); in tlb_entry_erase()
109 write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry); in tlb_entry_erase()
114 write_aux_reg(ARC_REG_TLBPD0, pd0); in tlb_entry_insert()
117 write_aux_reg(ARC_REG_TLBPD1, pd1); in tlb_entry_insert()
119 write_aux_reg(ARC_REG_TLBPD1, pd1 & 0xFFFFFFFF); in tlb_entry_insert()
120 write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32); in tlb_entry_insert()
123 write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry); in tlb_entry_insert()
142 write_aux_reg(ARC_REG_TLBPD1, 0); in local_flush_tlb_all()
145 write_aux_reg(ARC_REG_TLBPD1HI, 0); in local_flush_tlb_all()
147 write_aux_reg(ARC_REG_TLBPD0, 0); in local_flush_tlb_all()
151 write_aux_reg(ARC_REG_TLBINDEX, entry); in local_flush_tlb_all()
152 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI); in local_flush_tlb_all()
159 write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ); in local_flush_tlb_all()
162 write_aux_reg(ARC_REG_TLBINDEX, entry); in local_flush_tlb_all()
163 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWriteNI); in local_flush_tlb_all()
689 write_aux_reg(ARC_REG_TLBPD1HI, 0); in arc_mmu_init()
739 write_aux_reg(ARC_REG_TLBINDEX, in do_tlb_overlap_fault()
741 write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead); in do_tlb_overlap_fault()
772 write_aux_reg(ARC_REG_TLBINDEX, in do_tlb_overlap_fault()